EPC1PC8CC Datasheet EPC1PC8CC | P13-P15

Programming and Configuration File Support Page 13

Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation

Ta bl e 5 lists the programming adapter to use with each configuration device.

To program Altera configuration devices using the Quartus II software and the APU,

follow these steps:

1. Choose the Quartus II Programmer (Tools menu).

2. Load the appropriate .pof by clicking Add. The Device column displays the

device for the current programming file.

3. Insert a blank configuration device into the programming adapter’s socket.

4. Turn on the Program/Configure. You can also turn on Verify to verify the contents

of a programmed device against the programming data loaded from a

programming file.

5. Click Start.

6. After successful programming, you can place the configuration device on the PCB

to configure the FPGA device.

To program Altera configuration devices using the MAX+PLUS II software and the

APU, follow these steps:

1. Open the MAX+PLUS II Programmer.

2. Load the appropriate .pof using the Select Programming File dialog box (File

menu). By default, the Programmer loads the current project’s .pof. The Device

field displays the device for the current programming file.

3. Insert a blank configuration device into the programming adapter’s socket.

4. Click Program.

5. After successful programming, you can place the configuration device on the PCB

to configure the FPGA device.

If you are cascading EPC1 or EPC2 devices, you must generate multiple .pof. The first

device .pof have the same name as the project, while the second device .pof have the

same name as the first, but with a “_1” extension (e.g., top_1.pof).

Table 5. Programming Adapters

Device Package Adapter

EPC2

-pin J-Lead PLMJ1213

32-pin TQFP PLMT1213

EPC1

8-pin DIP PLMJ1213

20-pin J-Lead PLMJ1213

EPC1441

8-pin DIP PLMJ1213

20-pin J-Lead PLMJ1213

32-pin TQFP PLMT1064

Page 14 IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

The EPC2 device provides JTAG BST circuitry that complies with the IEEE Std.

1149.1-1990 specification. You can perform JTAG BST before or after configuration, but

not during configuration. Table 6 lists the JTAG instructions supported by the EPC2

device.

f For more information, refer to AN39: IEEE 1149.1 JTAG Boundary-Scan Testing in Altera

Devices.

Table 6. EPC2 Device JTAG Instructions

JTAG Instruction OPCODE Description

SAMPLE/PRELOAD 00 0101 0101

Allows a snapshot of a signal at the device pins to be captured and

examined during normal device operation and permits an initial data

pattern output at the device pins.

EXTEST 00 0000 0000

Allows the external circuitry and board-level interconnections to be

tested by forcing a test pattern at the output pins and capturing

results at the input pins.

BYPASS 11 1111 1111

Places the 1-bit bypass register between the

TDI

and

TDO

pins,

which allows the BST data to pass synchronously through a selected

device to adjacent devices during normal device operation.

IDCODE 00 0101 1001

Selects the device

IDCODE

TDI

and

TDO

pins, allowing the device

IDCODE

to be serially shifted out of

the

TDO

pin. The device

IDCODE

for the EPC2 configuration device is

shown below:

0000 0001000000000010 00001101110 1

USERCODE 00 0111 1001

Selects the USERCODE register and places it between the

TDI

and

TDO

pins, allowing the USERCODE to be serially shifted out of the

TDO

pin. The 32-bit USERCODE is a programmable user-defined

pattern.

INIT_CONF 00 0110 0001

Initiates the FPGA re-configuration process by pulsing the

INIT_CONF

pin low, which is connected to the FPGAs n

CONFIG

pins. After this instruction is updated, the n

INIT_CONF

pin is pulsed

low when the JTAG state machine enters the Run-Test/Idle state. The

INIT_CONF

pin is then released and

nCONFIG

is pulled high by the

resistor after the JTAG state machine goes out of Run-Test/Idle state.

The FPGA configuration starts after the n

CONFIG

pin goes high. As a

result, the FPGA is configured with the new configuration data stored

in the configuration device. You can add this function to your

programming file (.pof, .jam, .jbc) in the Quartus II software by

enabling the Initiate configuration after programming option in the

Programmer options window (Options menu). This instruction is

also used by the MAX+PLUS II software, .jam files, and .jbc files.

ISP Instructions —

These instructions are used when programming an EPC2 device

using JTAG ports with a USB-Blaster, MasterBlaster, ByteBlaster II,

EthernetBlaster, or ByteBlasterMV download cable, or using a .jam,

.jbc, or .svf file using an embedded processor.

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Page 15

Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation

Figure 4 shows the timing requirements for the JTAG signals.

Ta bl e 7 lists the timing parameters and values for configuration devices.

Figure 4. EPC2 Device JTAG Waveforms

Table 7. JTAG Timing Parameters and Values

Symbol Parameter Min Max Unit

JCP

TCK

clock period 100 — ns

JCH

TCK

clock high time 50 — ns

JCL

TCK

clock low time 50 — ns

JPSU

JTAG port setup time 20 — ns

JPH

JTAG port hold time 45 — ns

JPCO

JTAG port clock to output — 25 ns

JPZX

JTAG port high impedance to valid output — 25 ns

JPXZ

JTAG port valid output to high impedance — 25 ns

JSSU

Capture register setup time 20 — ns

JSH

Capture register hold time 45 — ns

JSCO

Update register clock to output — 25 ns

JSZX

Update register high impedance to valid output — 25 ns

JSXZ

Update register valid output to high impedance — 25 ns

TDO

TCK

JPZX

JPCO

JPH

JPXZ

JCP

JPSU

JCL

JCH

TDI

TMS

Signal

to be

Captured

Signal

to be

Driven

JSZX

JSSU

JSH

JSCO

JSXZ

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

EPC1PC8CC

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IC CONFIG DEVICE

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