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EPC1PC8CC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Operating Conditions Page 19
Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation
Operating Conditions
Ta bl e 1 2 through Ta bl e 1 9 list information about absolute maximum ratings,
recommended operating conditions, DC operating conditions, and capacitance for
configuration devices.
Table 12. Absolute Maximum Ratings
(1)
Symbol Parameter Conditions Min Max Unit
V
CC
Supply voltage With respect to GND
(2)
–2.0 7.0 V
V
I
DC input voltage With respect to GND
(2)
–2.0 7.0 V
I
MAX
DC V
CC
or GND current — — 50 mA
I
OUT
DC output current, per pin — –25 25 mA
P
D
Power dissipation — — 250 mW
T
STG
Storage temperature No bias –65 150 ° C
T
AMB
Ambient temperature Under bias –65 135 ° C
T
J
Junction temperature Under bias — 135 ° C
Table 13. Recommended Operating Conditions
Symbol Parameter Conditions Min Max Unit
V
CC
Supply voltage for 5.0-V operation
(3)
,
(4)
4.75
(4.50)
5.25
(5.50)
V
Supply voltage for 3.3-V operation
(3)
,
(4)
3.0 (3.0) 3.6 (3.6) V
V
I
Input voltage With respect to GND –0.3
V
CC
+ 0.3
(5)
V
V
O
Output voltage — 0 V
CC
V
T
A
Operating temperature
For commercial use 0 70 ° C
For industrial use –40 85 ° C
t
R
Input rise time — — 20 ns
t
F
Input fall time — — 20 ns
Table 14. DC Operating Conditions
Symbol Parameter Conditions Min Max Unit
V
IH
High-level input voltage — 2.0
V
CC
+ 0.3
(5)
V
V
IL
Low-level input voltage — –0.3 0.8 V
V
OH
5.0-V mode high-level TTL output
voltage
I
OH
= –4 mA DC
(6)
2.4 — V
3.3-V mode high-level CMOS
output voltage
I
OH
= –0.1 mA DC
(6)
V
CC
– 0.2 — V
V
OL
Low-level output voltage I
OL
= 4 mA DC
(6)
—0.4 V
I
I
Input leakage current V
I
= V
CC
or GND –10 10 A
I
OZ
Tri-state output off-state current V
O
= V
CC
or GND –10 10 A
Page 20 Operating Conditions
Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation
Table 15. EPC1064, EPC1064V, and EPC1213 Devices I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max
Unit
I
CC0
V
CC
supply current (standby) — — 100 200 A
I
CC1
V
CC
supply current (during configuration) — — 10 50 mA
Table 16. EPC2 Device Values
Symbol Parameter Conditions Min Typ Max Unit
I
CC0
V
CC
supply current (standby) V
CC
= 5.0 V or 3.3 V — 50 100 µA
I
CC1
V
CC
supply current (during
configuration)
V
CC
= 5.0 V or 3.3 V — 18 50 mA
R
CONF
Configuration pins
Internal pull up (
OE
, n
CS
,
n
INIT
_
CONF
)
—1—k
Table 17. EPC1 Device I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max Unit
I
CC0
V
CC
supply current (standby) — — 50 100 µA
I
CC1
V
CC
supply current (during configuration)
V
CC
= 5.0 V — 30 50 mA
V
CC
= 3.3 V — 10 16.5 mA
Table 18. EPC1441 Device I
CC
Supply Current Values
Symbol Parameter Conditions Min Typ Max Unit
I
CC0
V
CC
supply current (standby) — — 30 60 µA
I
CC1
V
CC
supply current (during configuration) V
CC
= 5.0 V — 15 30 mA
I
CC1
V
CC
supply current (during configuration) V
CC
= 3.3 V — 5 10 mA
Table 19. Capacitance
(7)
Symbol Parameter Conditions Min Max Unit
C
IN
Input pin capacitance V
IN
= 0 V, f = 1.0 MHz — 10 pF
C
OUT
Output pin capacitance V
OUT
= 0 V, f = 1.0 MHz — 10 pF
Notes to Table 12 through Ta ble 19 :
(1) For more information, refer to the Operating Requirements for Altera Devices Datasheet.
(2) The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for input currents less than
100 mA and periods shorter than 20 ns under no-load conditions.
(3) Numbers in parentheses are for industrial temperature range devices.
(4) Maximum V
CC
rise time is 100 ms.
(5) Certain EPC2 device pins are driven to 5.75 V when operated with a 3.3-V V
CC
. For more information, refer to Table 4 on page 11.
(6) The I
OH
parameter refers to high-level TTL or CMOS output current and the I
OL
parameter refers to low-level TTL or CMOS output current.
(7) Capacitance is sample tested only.
Pin Information Page 21
Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation
Pin Information
Ta bl e 2 0 lists the pin functions of the EPC1, EPC2, and EPC1441 devices during device
configuration.
f For more information about pin information of EPC devices, refer to the Enhanced
Configuration (EPC) Devices Datasheet.
f For more information about pin information of EPCS devices, refer to the Serial
Configuration (EPCS) Devices Datasheet.
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 1 of 3)
Pin Name
Pin Number
Pin Type Description
8-Pin
PDIP
(1)
20-Pin
PLCC
32-Pin
TQFP
(2)
DATA
1231Output
Serial data output. The
DATA
pin connects to the
DATA0
pin
of the FPGA.
DATA
is latched into the FPGA on the rising
edge of
DCLK
.
The
DATA
pin is tri-stated before configuration and when
the n
CS
pin is high. After configuration, the EPC2 device
drives
DATA
high, while the EPC1 and EPC1441 device
tri-state
DATA
.
DCLK
2 4 2 Bidirectional
Clock output when configuring with a single configuration
device or when the configuration device is the first
(master) device in a chain. Clock input for the next (slave)
configuration devices in a chain. The
DCLK
pin connects to
the
DCLK
pin of the FPGA.
Rising edges on
DCLK
increment the internal address
counter and present the next bit of data on the
DATA
pin.
The counter is incremented only if the
OE
input is held
high, the n
CS
input is held low, and all configuration data
has not been transferred to the target device.
After configuration or when
OE
is low, the EPC1, EPC2 and
EPC1441 device drive
DCLK
low.
OE
387
Open-drain
bidirectional
Output enable (active high) and reset (active low). The
OE
pin connects to the n
STATUS
pin of the FPGA.
A low logic level resets the address counter. A high logic
level enables
DATA
and the address counter to count. If this
pin is low (reset) during configuration, the internal
oscillator becomes inactive and
DCLK
drives low. For more
information, refer to “Error Detection Circuitry” on page 9.
The
OE
pin has an internal programmable 1-k resistor in
EPC2 devices. If internal pull-up resistors are used, do not
use external pull-up resistors on these pins. You can
disable the internal pull-up resistors through the Disable
nCS and OE pull-ups on configuration device option.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

EPC1PC8CC

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IC CONFIG DEVICE
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