EPC1PC8CC Datasheet EPC1PC8CC | P7-P9

Device Configuration Page 7

Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation

The EPC2 device’s

and

nCS

pins have internal programmable pull-up resistors. If

you use internal pull-up resistors, do not use external pull-up resistors on these pins.

The internal pull-up resistors are set by default in the Quartus II software. To turn off

the internal pull-up resistors, check the Disable nCS and OE pull-ups on

configuration device option when you generate programming files.

The configuration device’s

and

nCS

pins control the tri-state buffer on its

DATA

output pin and enable the address counter and oscillator. When the

pin is driven

low, the configuration device resets the address counter and tri-states its

DATA

pin. The

nCS

pin controls the

DATA

output of the configuration device. If the

nCS

pin is held high

after the

reset pulse, the counter is disabled and the

DATA

output pin is tri-stated. If

the

nCS

pin is driven low after the

reset pulse, the counter and

DATA

output pin are

enabled. When

is driven low again, the address counter is reset and the

DATA

output pin is tri-stated, regardless of the state of the

nCS

pin.

If the FPGA’s configuration data exceeds the capacity of a single EPC1 or EPC2

configuration device, you can cascade multiple EPC1 or EPC2 devices together. If

multiple EPC1 or EPC2 devices are required, the

nCASC

and

nCS

pins provide

handshaking between the configuration devices.

1 EPC1441 and EPC1064/EPC1064V devices cannot be cascaded.

When configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II,

FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices with

cascaded EPC1 or EPC2 devices, the position of the EPC1 or EPC2 device in the chain

determines its mode of operation. The first configuration device in the chain is the

master, while subsequent configuration devices are slaves. The

nINIT

CONF

pin of the

EPC2 master device can be connected to the

nCONFIG

pin of the FPGAs, which allows

the

INIT

CONF

JTAG instruction to begin FPGA configuration. The

nCS

pin of the

master configuration device is connected to the

CONF

DONE

pin of the FPGAs, while its

nCASC

pin is connected to the

nCS

pin of the next slave configuration device in the

chain. Additional EPC1 or EPC2 devices can be chained together by connecting the

nCASC

pin to the

nCS

pin of the next EPC1 or EPC2 slave device in the chain. The last

device’s

nCS

input comes from the previous device, while its

nCASC

pin is left floating.

All other configuration pins,

DCLK

DATA

, and

, are connected to every device in the

chain.

f For more information about configuration interface connections, including pull-up

resistor values, supply voltages, and

MSEL

pin setting, refer to the configuration

chapter in the appropriate device handbook.

Page 8 Device Configuration

Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation

Figure 3 shows the basic configuration interface connections between a configuration

device chain and the Altera FPGA.

When the first device in a configuration device chain is powered-up or reset, its

nCS

pin is driven low because it is connected to the

CONF

DONE

pin of the FPGA. Because

both

and

nCS

pins are low, the first device in the chain recognizes it as the master

device and controls configuration. Since the slave devices’

nCS

pin is fed by the

previous devices’

nCASC

pin, its

nCS

pin is high after power-up and reset. In the slave

configuration devices, the

DATA

output is tri-stated and

DCLK

is an input. During

configuration, the master device supplies the clock through

DCLK

to the FPGA and to

any slave configuration devices. The EPC1 or EPC2 master device also provides the

first stream of data to the FPGA during multi-device configuration. After the EPC1 or

EPC2 master device finishes sending configuration data, it tri-states its

DATA

pin to

avoid contention with other configuration devices. The EPC1 or EPC2 master device

also drives its

nCASC

pin low, which pulls the

nCS

pin of the next device low. This

action signals the EPC1 or EPC2 slave device to start sending configuration data to the

FPGAs.

The EPC1 or EPC2 master device clocks all slave configuration devices until

configuration is complete. When all configuration data is transferred and the

nCS

on the EPC1 or EPC2 master device is driven high by the FPGA’s

CONF

DONE

pin, the

EPC1 or EPC2 master device then goes into zero-power (idle) state. The EPC2 master

device drives

DATA

high and

DCLK

low, while the EPC1 and EPC1441 device tri-state

DATA

and drive

DCLK

low.

If the

nCS

pin on the EPC1 or EPC2 master device is driven high before all

configuration data is transferred, the EPC1 or EPC2 master device drives its

signal

low, which in turn drives the FPGA’s

nSTATUS

pin low, indicating a configuration

error. Additionally, if the configuration device generates its data and detects that the

CONF

DONE

pin has not gone high, it recognizes that the FPGA has not configured

successfully. EPC1 and EPC2 devices wait for 16

DCLK

cycles after the last

Figure 3. Altera FPGA Configured Using Two EPC1 or EPC2 Configuration Devices

(1)

Notes to Figure 3:

(1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook.

(2) The n

INIT

CONF

pin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up

resistor is not required on the n

INIT

CONF

CONFIG

line. The n

INIT

CONF

pin does not need to be connected if its functionality is not used.

If the n

INIT

CONF

pin is not used or unavailable, n

CONFIG

must be pulled to V

either directly or through a resistor.

(3) EPC2 devices have internal programmable pull-up resistors on

and n

pins. If internal pull-up resistors are used, do not use external pull-up

resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check

the Disable nCS and OE pull-ups on configuration device option when you generate programming files.

GND

DCLK

DATA

nCS

FPGA

MSEL

DCLK

DATA0

nSTATUS

CONF_DONE

nCONFIG

nCE

Master

Configuration

Device

Slave

Configuration

Device

DCLK

DATA

OE (3)

nCS (3)

nINIT_CONF

(2)

nCASC

N.C.

nCEO

N.C.

(2)(3) (3)

Power and Operation Page 9

Configuration Devices for SRAM-Based LUT DevicesJanuary 2012 Altera Corporation

configuration bit was sent for the

CONF

DONE

pin to reach a high state. In this case, the

configuration device pulls its

pin low, which in turn drives the target device’s

nSTATUS

pin low. Configuration automatically restarts if the Auto-restart

configuration on error option is turned on in the Quartus II software from the

General tab of the Device & Pin Options dialog box or the MAX+PLUS II software’s

Global Project Device Options dialog box (Assign menu).

f For more information about FPGA configuration and configuration interface

connections between configuration devices and Altera FPGAs, refer to the

configuration chapter in the appropriate device handbook.

Power and Operation

This section describes power-on reset (POR) delay, error detection, and 3.3-V and

5.0-V operation of Altera configuration devices.

Power-On Reset

During initial power-up, a POR delay occurs to permit voltage levels to stabilize.

When configuring an FPGA with one EPC1, EPC2, or EPC1441 device, the POR delay

occurs inside the configuration device and the POR delay is a maximum of 200 ms.

When configuring a FLEX 8000 device with one EPC1213, EPC1064, or EPC1064V

device, the POR delay occurs inside the FLEX 8000 device and the POR delay is

typically 100 ms, with a maximum of 200 ms.

During POR, the configuration device drives its

pin low. This low signal delays

configuration because the

pin is connected to the target FPGA’s

nSTATUS

pin. When

the configuration device completes POR, it releases its open-drain

pin, which is

then pulled high by a pull-up resistor.

1 You should power up the FPGA before the configuration device exits POR to avoid

the master configuration device from entering slave mode.

If the FPGA is not powered up before the configuration device exits POR, the

CONF

DONE

nCS

line is high because of the pull-up resistor. When the configuration

device exits POR and releases

, it sees

nCS

high, which signals the configuration

device to enter slave mode. Therefore, configuration will not begin because the

DATA

output is tri-stated and

DCLK

is an input pin in slave mode.

Error Detection Circuitry

The EPC1, EPC2, and EPC1441 configuration devices have built-in error detection

circuitry for configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,

Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, or

Stratix II GX devices.

Built-in error detection circuitry uses the

nCS

pin of the configuration device, which

monitors the

CONF

DONE

pin on the FPGA. If the

nCS

pin on the EPC1 or EPC2 master

device is driven high before all configuration data is transferred, the EPC1 or EPC2

master device drives its

signal low, which in turn drives the FPGA’s

nSTATUS

low, indicating a configuration error. Additionally, if the configuration device

generates its data and detects that the

CONF

DONE

pin has not gone high, it recognizes

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EPC1PC8CC

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IC CONFIG DEVICE

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