Page 18 Timing Information
Configuration Devices for SRAM-Based LUT Devices January 2012 Altera Corporation
Ta bl e 11 lists the timing parameters when using EPC1, EPC1064, EPC1064V, EPC1213,
and EPC1441 devices when configuring the FLEX 8000 device.
t
OEW
OE
low pulse width (reset) to guarantee counter reset 100 — — ns
t
OEC
OE
low (reset) to
DCLK
disable delay — — 20 ns
t
NRCAS
OE
low (reset) to n
CASC
delay — — 25 ns
Note to Tabl e 10 :
(1) During initial power-up, a POR delay occurs to permit voltage levels to stabilize. Subsequent reconfigurations do not incur this delay.
Table 10. Timing Parameters when Using EPC1, EPC2, and EPC1441 Devices at 5.0 V (Part 2 of 2)
Symbol Parameter Min Typ Max Units
Table 11. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1064, EPC1064V, EPC1213, and EPC1441
Devices
Symbol Parameter
EPC1064V
EPC1064 and
EPC1213
EPC1 and
EPC1441
Unit
Min Max Min Max Min Max
t
OEZX
OE
high to
DATA
output enabled — 75 — 50 — 50 ns
t
CSZX
n
CS
low to
DATA
output enabled — 75 — 50 — 50 ns
t
CSXZ
n
CS
high to
DATA
output disabled — 75 — 50 — 50 ns
t
CSS
n
CS
low setup time to first
DCLK
rising edge 150 — 100 — 50 — ns
t
CSH
n
CS
low hold time after
DCLK
rising edge 0—0—0—ns
t
DSU
Data
setup time before rising edge on
DCLK
75 — 50 — 50 — ns
t
DH
Data
hold time after rising edge on
DCLK
0—0—0—ns
t
CO
DCLK
to
DATA
out delay — 100 — 75 — 75 ns
t
CK
Clock period 240 — 160 — 100 — ns
f
CK
Clock frequency — 4 — 6 — 8 MHz
t
CL
DCLK
low time 120 — 80 — 50 — ns
t
CH
DCLK
high time 120 — 80 — 50 — ns
t
XZ
OE
low or n
CS
high to
DATA
output disabled — 75 — 50 — 50 ns
t
OEW
OE
pulse width to guarantee counter reset 150 — 100 — 100 — ns
t
CASC
Last
DCLK
+ 1 to n
CASC
low delay — 90 — 60 — 50 ns
t
CKXZ
Last
DCLK
+ 1 to
DATA
tri-state delay — 75 — 50 — 50 ns
t
CEOUT
n
CS
high to n
CASC
high delay — 150 — 100 — 100 ns
