February 1996
NDS8852H
Complementary MOSFET Half Bridge
General Description Features
________________________________________________________________________________
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter N-Channel P-Channel Units
V
DSS
Drain-Source Voltage 30 -30 V
V
GSS
Gate-Source Voltage 20 -20 V
I
D
Drain Current - Continuous (Note 1a & 2) 4.3 -3.4 A
- Pulsed 15 -10
P
D
Maximum Power Dissipation (Note 1a) 2.5 W
(Single Device) (Note 1b) 1.2
(Note 1c) 1
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient
(Single Device) (Note 1a)
50 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case
(Single Device) (Note 1)
25 °C/W
NDS8852H Rev. C1
These Complementary MOSFET half bridge devices are
produced using Fairchild's proprietary, high cell density,
DMOS technology. This very high density process is
especially tailored to minimize on-state resistance, provide
superior switching performance, and withstand high energy
pulses in the avalanche and commutation modes. These
devices are particularly suited for low voltage half bridge
applications or CMOS applications when both gates are
connected together.
N-Channel 4.3A, 30V, R
DS(ON)
=0.08 @ V
GS
=10V.
P-Channel -3.4A, -30V, R
DS(ON)
=0.13@ V
GS
=-10V.
High density cell design or extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Matched pair for equal input capacitance and power capability
.
P-Gate
Vout
Vout
Vout
Vout
V-
V+
N-Gate
© 1997 Fairchild Semiconductor Corporation
Electrical Characteristics (T
A
= 25°C unless otherwise noted)
Symbol Parameter Conditions Type Min Typ Max Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage V
GS
= 0 V, I
D
= 250 µA N-Ch 30 V
V
GS
= 0 V, I
D
= -250 µA
P-Ch -30 V
I
DSS
Zero Gate Voltage Drain Current V
DS
= 24 V, V
GS
= 0 V N-Ch 2 µA
T
J
= 55
o
C
25 µA
V
DS
= -24 V, V
GS
= 0 V P-Ch -2 µA
T
J
= 55
o
C
-25 µA
I
GSSF
Gate - Body Leakage, Forward V
GS
= 20 V, V
DS
= 0 V All 100 nA
I
GSSR
Gate - Body Leakage, Reverse
V
GS
= -20 V, V
DS
= 0 V
All -100 nA
ON CHARACTERISTICS (Note 3)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250 µA
N-Ch 1 1.7 2.8 V
T
J
= 125
o
C
0.7 1.2 2.2
V
DS
= V
GS
, I
D
= -250 µA
P-Ch -1 -1.6 -2.8
T
J
= 125
o
C
-0.85 -1.25 -2.5
R
DS(ON)
Static Drain-Source On-Resistance
V
GS
= 10 V, I
D
= 3.4 A
N-Ch 0.06 0.08
T
J
= 125
o
C 0.08 0.13
V
GS
= 4.5 V, I
D
= 2.8 A
0.08 0.11
V
GS
= -10 V, I
D
= -3.4 A P-Ch 0.11 0.13
T
J
= 125
o
C
0.15 0.21
V
GS
= -4.5 V, I
D
= -2.8 A 0.17 0.2
I
D(on)
On-State Drain Current
V
GS
= 10 V, V
DS
= 5 V
N-Ch 10 A
V
GS
= -10 V, V
DS
= -5 V P-Ch -10
g
FS
Forward Transconductance
V
DS
= 15 V, I
D
= 3.4 A
N-Ch 6 S
V
DS
= -15 V, I
D
= -3.4 A P-Ch 4
DYNAMIC CHARACTERISTICS
C
iss
Input Capacitance N-Channel
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
P-Channel
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
N-Ch 300 pF
P-Ch 330
C
oss
Output Capacitance N-Ch 190 pF
P-Ch 190
C
rss
Reverse Transfer Capacitance N-Ch 70 pF
P-Ch 70
NDS8852H Rev. C1
Electrical Characteristics (T
A
= 25°C unless otherwise noted)
Symbol Parameter Conditions Type Min Typ Max Units
SWITCHING CHARACTERISTICS (Note 3)
t
D(on)
Turn - On Delay Time N-Channel
V
DD
= 10 V, I
D
= 1 A,
V
GEN
= 10 V, R
GEN
= 6
P-Channel
V
DD
= -10 V, I
D
= -1 A,
V
GEN
= -10 V, R
GEN
= 6
N-Ch 10 15 ns
P-Ch 9 40
t
r
Turn - On Rise Time N-Ch 13 20 ns
P-Ch 21 40
t
D(off)
Turn - Off Delay Time N-Ch 21 50 ns
P-Ch 21 90
t
f
Turn - Off Fall Time N-Ch 5 50 ns
P-Ch 8 50
Q
g
Total Gate Charge N-Channel
V
DS
= 10 V,
I
D
= 3.4 A, V
GS
= 10 V
P-Channel
V
DS
= -10 V,
I
D
= -3.4 A, V
GS
= -10 V
N-Ch 9.5 27 nC
P-Ch 10 25
Q
gs
Gate-Source Charge N-Ch 1.5
P-Ch 1.6
Q
gd
Gate-Drain Charge N-Ch 2.6
P-Ch 2.7
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 2.1 A
P-Ch -2.1
V
SD
Drain-Source Diode Forward
Voltage
V
GS
= 0 V, I
S
= 2.1 A
(Note 2) N-Ch 0.8 1.2 V
V
GS
= 0 V, I
S
= -2.1 A
(Note 2)
P-Ch -0.8 -1.2
t
rr
Reverse Recovery Time N-Channel
V
GS
= 0 V, I
F
= 2.1 A, dI
F
/dt = 100 A/µs
N-Ch 100 ns
P-Channel
V
GS
= 0 V, I
F
= -2.1 A, dI
F
/dt = 100 A/µs
P-Ch 100
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(
t
)
=
T
J
T
A
R
θJ A
(t)
=
T
J
T
A
R
θ
J C
+R
θ
CA
(
t
)
= I
D
2
(t) × R
DS (ON ) T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 50
o
C/W when mounted on a 1 in
2
pad of 2oz cpper.
b. 105
o
C/W when mounted on a 0.04 in
2
pad of 2oz cpper.
c. 125
o
C/W when mounted on a 0.006 in
2
pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8852H Rev. C1
1a
1b
1c

NDS8852H

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
MOSFET DISC BY MFG 2/02
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet