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843441AM-150LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
1©2016 Integrated Device Technology, Inc June 30, 2016
General Description
The 843441 is a low jitter, high performance clock generator. The
843441 is designed for use in applications using the SAS and SATA
interconnect. The 843441 uses an external, 25MHz, parallel
resonant crystal to generate four selectable output frequencies:
75MHz, 100MHz, 150MHz, and 300MHz. This silicon based
approach provides excellent frequency stability and reliability. The
843441 features down and center spread spectrum (SSC) clocking
techniques.
Additional Ordering Information
Features
• Designed for use in SAS, SAS-2, and SATA systems
• Center (±0.33%) Spread Spectrum Clocking (SSC)
• Down (-0.30% or -0.60%) SSC
• Better frequency stability than SAW oscillators
• One differential 3.3V LVPECL output
• Crystal oscillator interface designed for 25MHz
(C
L
= 18pF) frequency
• External fundamental crystal frequency ensures high reliability
and low aging
• Selectable output frequencies: 75MHz, 100MHz, 150MHz,
300MHz
• Output frequency is tunable with external capacitors
• RMS phase jitter: 1.33ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in lead-free (RoHS 6) package
• 843441-150 Functional replacement part use 8T49N242i
Part/Order Number Package Output Frequency
(MHz)
843441AG 16 TSSOP 75, 100, 150, 300
843441AM-75 8 SOIC 75
843441AM-100 8 SOIC 100
843441AM-150 8 SOIC 150
843441AM-300 8 SOIC 300
Block Diagrams
FemtoClock
PLL
OSC
nPLL_SEL
1
0
25MHz
XTAL
XTAL_IN
XTAL_OUT
00 = 75MHz
01 = 100MHz
10 = 150MHz
(default)
11 = 300MHz
Q
nQ
SSC_SEL(1:0)
F_ S E L( 1: 0)
SSC Output
Control Logic
16- Lead TSSOP
FemtoClock
PLL
OSC
25MHz
XTAL
XTAL_IN
XTAL_OUT
Q
nQ
SSC_SEL(1:0)
SSC Output
Control Logic
8-Lead SOIC
Pulldown
Pullup:Pulldown
Pulldown:
Pulldown
Pulldown:
Pulldown
Pin Assignments
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
SSC_SEL0
XTAL_IN
XTAL_OUT
V
EE
F_SEL1
nPLL_SEL
nQ
Q
V
CC
F_SEL0
V
C
C
SSC_SEL1
V
EE
nc
nc
843441
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
843441
8-Lead SOIC, 150 Mil
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
843441-150 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
843441
Data Sheet
FemtoClock® SAS/SATA Clock
Generator
2©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Table 1A. Pin Descriptions (SOIC Package)
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 1B. Pin Descriptions (TSSOP Package)
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1,
2
XTAL_OUT,
XTAL_IN
Input Pullup Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3,
4
SSC_SEL0,
SSC_SEL1
Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
5V
CC
Power Power supply pin.
6, 7 Q, nQ Output Differential clock outputs. LVPECL interface levels.
8V
EE
Power Negative supply pin.
Number Name Type Description
1, 15 V
EE
Power Negative supply pins.
2,
3
XTAL_OUT,
XTAL_IN
Input Pullup Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
4,
8
SSC_SEL0,
SSC_SEL1
Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
5, 6, 7 nc Unused No connect pins.
9, 11 V
CC
Power Power supply pins.
10 F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
12, 13 Q, nQ Output Differential clock outputs. LVPECL interface levels.
14 nPLL_SEL Input Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels.
16 F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
3©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Table 3B. F_SEL[1:0] Function Table
Table 3B applicable only for 16 Lead TSSOP package.
Inputs
ModeSSC_SEL1 SSC_SEL0
0 (default) 0 (default) SSC Off
0 1 0.60% Down-spread
1 0 0.30% Down-spread
1 1 0.33% Center-spread
Inputs
Output Frequency (MHz)F_SEL1 F_SEL0
00 75
01 100
1 (default) 0 (default) 150
11 300
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

843441AM-150LFT

Mfr. #:
Buy 843441AM-150LFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock SAS/SATA Clock Generator
Lifecycle:
New from this manufacturer.
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