7©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
Output Rise/Fall Time
Cycle-to-Cycle Jitter
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
RMS Period Jitter, Peak-to-Peak
SCOPE
Qx
nQx
V
EE
V
CC
2V
-1.3V ± 0.165V
nQ
Q
nQ
Q
nQ
Q
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
10,000 cycles
Reference Point
(Trigger Edge)
Histogram
t jit (pk-pk)
8©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50
. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC
XTAL_OUT
XTAL_IN
R1
100
R2
100
Zo = 50 ohmsRs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTA L_ OU T
XTA L_ I N
Zo = 50 ohms
C2
.1uf
LVPECL Driver
Zo = 50 ohms
R1
50
R2
50
R3
50
9©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_

843441AM-150LFT

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Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock SAS/SATA Clock Generator
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