OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

843441AM-150LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
10©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Schematic Example
Figure 3 shows an example of 843441 application schematic. In this
example, the device is operated at V
CC
= 3.3V. An 18pF parallel
resonant 25MHz crystal is used. The load capacitance C1 = 27pF
and C2 = 27pF are recommended for frequency accuracy.
Depending on the parasitics of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used. This will required adjusting C1 and C2.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 843441 provides separate
power supplies to isolate noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitances in the local area of all
devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 3. 843441 Schematic Example
Optional
Y-Termination
Set Logic
Input to
'1'
C5
10uF
C2
27pF
R6
50
Zo = 50 Ohm
Logic Control Input Examples
+
-
SSC_SEL1
U1
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
VEE
XTAL_OUT
XTAL_IN
SSC_SEL0
nc
nc
nc
SSC_SEL1 VCC
F_SEL0
VCC
Q
nQ
nPLL_SEL
VEE
F_SEL1
XTAL_IN
BLM18BB221SN1
Ferrite Bead
1 2
RU1
1K
3.3V
XTAL_OUT
VCC
LVPECL Termination
F_SEL0
RD2
1K
nPLL_SEL
R2
133
Q
C3
0.1uF
To Logic
Input
pins
SSC_SEL0
R5
50
nQ
C1
27pF
R4
82.5
F_SEL1
RD1
Not Install
R7
50
R3
82.5
RU2
Not Install
+
-
Set Logic
Input to
'0'
C4
0.1uF
VCC
Zo = 50 Ohm
3.3V
R1
133
X1
25MHz
To Logic
Input
pins
C6
0.1uF
Zo = 50 Ohm
Zo = 50 Ohm
VCC
11©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Peak-to-Peak Jitter Calculations
A standard deviation of a statistical population or data set is the
square root of its variance. A standard deviation is used to calculate
the probability of an anomaly or to predict a failure. Many times, the
term "root mean square" (RMS) is used synonymously for standard
deviation. This is accurate when referring to the square root of the
mean squared deviation of a signal from a given baseline and the
data set contains a Gaussian distribution with no deterministic
components. A low standard deviation indicates that the data set
tends to be close to the mean with little variation. A large standard
deviation indicates that the data set is spread out and has a large
variation from the mean.
A standard deviation is required when calculating peak-to-peak jitter.
Since true peak-to-peak jitter is random and unbounded, it is
important to always associate a bit error ratio (BER) when specifying
a peak-to-peak jitter limit. Without it, the specification is
meaningless. Given that a BER is application specific, many
frequency timing devices specify jitter as an RMS. This allows the
peak-to-peak jitter to be calculated for the specific application and
BER requirement. Because a standard deviation is the variation
from the mean of the data set, it is important to always calculate the
peak-to-peak jitter using the typical RMS value.
The table shows the BER with its appropriate RMS Multiplier. Once
the BER is chosen, the peak to peak jitter can be calculated by
simply multiplying the RMS multiplier with the typical RMS datasheet
specification. For example, if a 10
-12
BER is required, multiply
14.260 times the typical jitter specification.
Jitter (peak-to-peak) = RMS Multiplier x RMS (typical)
This calculation is not specific to one type of Jitter classification. It
can be used to calculate BER on various types of RMS jitter. It is
important that the user understands their jitter requirement to ensure
they are calculating the correct BER for their jitter requirement.
BER RMS Multiplier
10
-3
6.582
10
-4
7.782
10
-5
8.834
10
-6
9.784
10
-7
10.654
10
-8
11.462
10
-9
12.218
10
-10
12.934
10
-11
13.614
10
-12
14.260
10
-13
14.882
10
-14
15.478
10
-15
16.028
12©2016 Integrated Device Technology, Inc June 30, 2016
843441 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 843441.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843441 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 66mA = 228.69mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power_
MAX
(3.465V, with all outputs switching) = 228.69mW + 30mW = 258.69mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 96°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.259W * 96°C/W = 94.864°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance
JA
for 16 Lead TSSOP, Forced Convection
Table 6B. Thermal Resistance
JA
for 8 Lead SOIC, Forced Convection
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W
JA
vs. Air Flow
Linear Feet per Second 0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

843441AM-150LFT

Mfr. #:
Buy 843441AM-150LFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products FemtoClock SAS/SATA Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet