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DS2782G+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
DS2782
19 of 28
STATUS REGISTER
The STATUS register contains bits which report the device status. The bits can be set internally by the DS2782.
The CHGTF, AEF, SEF, LEARNF and VER bits are read only bits which can be cleared by hardware. The UVF and
PORF bits can only be cleared via the 2-Wire interface.
Figure 18. Status Register Format
ADDRESS 01h BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUES
CHGTF
7 Read Only
Charge Termination Flag
Set to 1 when: ( VOLT > VCHG ) AND ( 0 < IAVG < IMIN ) continuously
for a period between two IAVG register updates ( 28s to 56s ).
Cleared to 0 when: RARC < 90%
AEF
6 Read Only
Active Empty Flag
Set to 1 when: VOLT < VAE
Cleared to 0 when: RARC > 5%
SEF
5 Read Only
Standby Empty Flag
Set to 1 when: RSRC < 10%
Cleared to 0 when: RSRC > 15%
LEARNF
4 Read Only
Learn Flag – When set to 1, a charge cycle can be used to learn battery
capacity.
Set to 1 when: ( VOLT falls from above VAE to below VAE ) AND
( CURRENT > IAE )
Cleared to 0 when: ( CHGTF = 1 ) OR ( CURRENT < +100µV ) OR
( ACR = 0 **) OR ( ACR written or recalled from EEPROM) OR ( SLEEP
Entered )
Reserved
3 Read Only Undefined
UVF
2 Read / Write *
Under-Voltage Flag
Set to 1 when: VOLT < V
SLEEP
Cleared to 0 by: User
PORF
1 Read / Write *
Power-On Reset Flag – Useful for reset detection, see text below.
Set to 1 upon Power-Up by hardware.
Cleared to 0 by: User
Reserved
0 Read Only Undefined
* - This bit can be set by the DS2782, and may only be cleared via the 2-Wire interface.
** - LEARNF is only cleared if ACR reaches 0 after VOLT < VAE.
DS2782
20 of 28
CONTROL REGISTER
All CONTROL register bits are read and write accessible. The CONTROL register is recalled from Parameter
EEPROM memory at power-up. Register bit values can be modified in shadow RAM after power-up. Shadow RAM
values can be saved as the power up default values by using the Copy Data command.
Figure 19. Control Register Format
ADDRESS 60h BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUEs
Reserved
7 Undefined
UVEN
6 Read/Write
Under Voltage SLEEP Enable
0: Disables transition to SLEEP mode based on VIN voltage
1: Enables transition to SLEEP mode if,
VIN < V
SLEEP
AND SDA, SCL stable at either logic level for t
SLEEP
PMOD
5 Read/Write
Power Mode Enable
0: Disables transition to SLEEP mode based on SDA, SCL logic state
1: Enables transition to SLEEP mode if SDA, SCL at a logic low for
t
SLEEP
Reserved
0:4 Undefined
SPECIAL FEATURE REGISTER
All Special Feature Register bits are read and write accessible, with default values specified in each bit definition.
Figure 20. Special Feature Register Format
ADDRESS 15h BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUES
Reserved
2:7 Undefined
SAWE
1 Read/Write
Slave Address Write Enable
0: Disables writes to the Slave Address Register
1: Enables writes to the Slave Address Register
Power-up default: 0 (writes disabled)
PIOSC
0 Read/Write
PIO Sense and Control
Read values
0: PIO pin ≤ Vil
1: PIO pin ≥ Vih
Write values
0: Activates PIO pin open-drain output driver, forcing the PIO pin low
1: Disables the output driver, allowing the PIO pin to be pulled high or
used as an input
Power-up and SLEEP mode default: 1 (PIO pin is hi-Z)
Note: PIO pin has weak pulldown
DS2782
21 of 28
EEPROM REGISTER
The EEPROM register provides access control of the EEPROM blocks. EEPROM blocks can be locked to prevent
alteration of data within the block. Locking a block disables write access to the block. Once a block is locked, it
cannot be unlocked. Read access to EEPROM blocks is unaffected by the lock/unlock status.
Figure 21. EEPROM Register Format
ADDRESS 1Fh BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUES
EEC
7 Read Only
EEPROM Copy Flag
Set to 1 when: Copy Data command executed
Cleared to 0 when: Copy Data command completes
Note: While EEC = 1, writes to EEPROM addresses are ignored
Power-up default: 0
LOCK
6
Read /
Write to 1
EEPROM Lock Enable
Host write to 1: Enables the Lock command. Host must issue Lock
command as next command after writing Lock Enable bit to 1.
Cleared to 0 when: Lock command completes or when Lock command
not the command issued immediately following the Write command
used to set the Lock Enable bit.
Power-up default: 0
Reserved
2:6 Undefined
BL1
1 Read Only
EEPROM Block 1 Lock Flag (Parameter EEPROM 60h – 7Fh)
0: EEPROM is not locked
1: EEPROM block is locked
Factory default: 0
BL0
0 Read Only
EEPROM Block 0 Lock Flag (User EEPROM 20h – 2Fh)
0: EEPROM is not locked
1: EEPROM block is locked
Factory default: 0
PROGRAMMABLE SLAVE ADDRESS
The 2-Wire slave address of the DS2782 is stored in the parameter EEPROM block, address 7Eh. Programming
the slave address requires a write to set the SAWE (Slave Address Write Enable) bit in the Special Features
register, followed by a write to 7Eh with the desired slave address. The new slave address value is effective
following the write to 7Eh, and must be used to address the DS2782 on subsequent bus transactions. The slave
address value is not stored to EEPROM until a Copy EEPROM block 1 command is executed. Prior to executing
the Copy command, power cycling the DS2782 restores the original slave address value. The data format of the
slave address value in address 7Eh is shown in Figure 22. When not writing the slave address, the SAWE bit
should be written to a 0.
Figure 22. Slave Address Format
ADDRESS 7Eh
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
A6 A5 A4 A3 A2 A1 A0 X
A6-A0: Slave Address. A6-A0 contains the 7-bit slave address of the DS2782. The factory default is 0110100b.
X: Reserved Bits.
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DS2782G+

Mfr. #:
Buy DS2782G+
Manufacturer:
Maxim Integrated
Description:
Battery Management Stand-Alone Fuel Gauge
Lifecycle:
New from this manufacturer.
Delivery:
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