DS2782G+ Datasheet DS2782G+, DS2782E+ | P25-P27

DS2782

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Acknowledge Bits

Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the

master and the DS2782 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must

pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL

returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of

the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits

allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is

busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re-

attempt communication.

Data Order

A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is

followed by the Acknowledge bit. DS2782 registers composed of multi-byte values are ordered most significant

byte (MSB) first. The MSB of multi-byte registers is stored on even data memory addresses.

Slave Address

A bus master initiates communication with a slave device by issuing a START condition followed by a Slave

Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2782 continuously monitors for a

START condition followed by its slave address. When the DS2782 receives a slave address that matches the value

in its Programmable Slave Address register, it responds with an Acknowledge bit during the clock period following

the R/W bit. The 7-bit Programmable Slave Address register is factory programmed to 0110100. The slave address

can be re-programmed, refer to the Programmable Slave Address section for details.

Read/Write Bit

The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0

selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read

transaction, with the following bytes being read from the stave by the master.

Bus Timing

The DS2782 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any

speed.

2-Wire Command Protocols

The command protocols involve several transaction formats. The simplest format consists of the master writing the

START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2782. More

complex formats such as the Write Data, Read Data and Function command protocols write data, read data and

execute device specific operations. All bytes in each command format require the slave or host to return an

Acknowledge bit before continuing with the next byte. Each function command definition outlines the required

transaction format. The following key applies to the transaction formats.

Table 4. 2-Wire Protocol Key

KEY DESCRIPTION KEY DESCRIPTION

S START bit Sr Repeated START

SAddr Slave Address (7-bit) W R/W bit = 0

FCmd Function Command byte R R/W bit = 1

MAddr Memory Address byte P STOP bit

Data Data byte written by master Data Data byte returned by slave

A Acknowledge bit - Master A Acknowledge bit - Slave

N No Acknowledge - Master N No Acknowledge - Slave

DS2782

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Basic Transaction Formats

Write: S SAddr W A MAddr A Data0 A P

A write transaction transfers one or more data bytes to the DS2782. The data transfer begins at the memory

address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction,

except for the Acknowledge cycles.

Read: S SAddr W A MAddr A Sr SAddr R A Data0 N P

Write Portion Read Portion

A read transaction transfers one or more bytes from the DS2782. Read transactions are composed of two parts, a

write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write portion

communicates the starting point for the read operation. The read portion follows immediately, beginning with a

Repeated START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2782 beginning with

the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2782 throughout the

transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding

to the last byte it requires with a No Acknowledge. This signals the DS2782 that control of SDA is to remain with

the master following the Acknowledge clock.

Write Data Protocol

The write data protocol is used to write to register and shadow RAM data to the DS2782 starting at memory

address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and

DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by

sending a STOP or Repeated START after receiving the last acknowledge bit.

S SAddr W A MAddr A Data0 A Data1 A … DataN A P

The msb of the data to be stored at address MAddr can be written immediately after the MAddr byte is

acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is

received by the DS2782, the msb of the data at address MAddr + 1 is can be written immediately after the

acknowledgement of the data at address MAddr. If the bus master continues an auto-incremented write transaction

beyond address 4Fh, the DS2782 ignores the data. Data is also ignored on writes to read-only addresses and

reserved addresses, locked EEPROM blocks as well as a write that auto increments to the Function Command

memory. As noted in the Memory Section, writes to unlocked EEPROM blocks modify the shadow RAM only.

Read Data Protocol

The Read Data protocol is used to read register and shadow RAM data from the DS2782 starting at memory

address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data

from MAddr + 1 and DataN represents the last byte read by the master.

S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A … DataN N P

Data is returned beginning with the most significant bit (msb) of the data in MAddr. Because the address is

automatically incremented after the least significant bit (lsb) of each byte is returned, the msb of the data at

address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If

the bus master continues to read beyond address FFh, the DS2782 outputs data values of FFh. Addresses labeled

“Reserved” in the memory map return undefined data. The bus master terminates the read transaction at any byte

boundary by issuing a No Acknowledge followed by a STOP or Repeated START.

Function Command Protocol

The Function Command protocol executes a device specific operation by writing one of the function command

values (FCmd) to memory address FEh. Table 5 lists the DS2782 FCmd values and describes the actions taken by

each. A one byte write protocol is used to transmit the function command, with the MAddr set to FEh and the data

byte set to the desired FCmd value. Additional data bytes are ignored. Data read from memory address FEh is

undefined. S SAddr W A MAddr=0FEh A FCmd A P

DS2782

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Table 5. Function Commands

FUNCTION

COMMAND

TARGET

EEPROM

BLOCK

FCMD

VALUE

DESCRIPTION

0 42h

Copy Data

1 44h

This command copies the shadow RAM to the target EEPROM block.

Copy Data commands that target locked blocks are ignored. While the

Copy Data command is executing, the EEC bit in the EEPROM register is

set to 1, and Write Data commands with MAddr set to any address within

the target block are ignored. Read Data and Write Data commands with

MAddr set outside the target block are processed while the copy is in

progress. The Copy Data command execution time, t

EEC

, is 2ms typical

and starts after the FCMD byte is acknowledged. Subsequent Copy or

Lock commands must be delayed until the EEPROM programming cycle

completes.

0 B2h

Recall Data

1 B4h

This command recalls the contents of the targeted EEPROM block to its

shadow RAM.

0 63h

Lock

1 66h

This command locks (write-protects) the targeted EEPROM block. The

LOCK bit in the EEPROM register must be set to 1 before the lock

command is executed. If the LOCK bit is 0, the lock command has no

effect. The lock command is permanent; a locked block can never be

written again. The Lock command execution time, t

EEC

, is 2ms typical and

starts after the FCMD byte is acknowledged. Subsequent Copy or Lock

commands must be delayed until the EEPROM programming cycle

completes.

64-BIT UNIQUE ID

The DS2782 can be special ordered with a unique, factory-programmed ID that is 64 bits in length. The first eight

bits are the product family code (B2h for DS2782). The next 48 bits are a unique 40-bit serial number followed by

0x82h. The last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 24). The 64-bit ID

can be read as 8 bytes starting at memory address F0h. The 64-bit ID is read only.

Figure 24. 64-Bit ID Format

8-BIT CRC 48-BIT SERIAL NUMBER

8-BIT FAMILY

CODE (B2h)

msb lsb

PACKAGE INFORMATION

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

8 TSSOP H8+2

21-0175

10 TDFN-EP T1034+1

21-0268

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

DS2782G+

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Battery Management Stand-Alone Fuel Gauge

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DS2782G+

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