DS2782G+ Datasheet DS2782G+, DS2782E+ | P22-P24

DS2782

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MEMORY

The DS2782 has a 256 byte linear memory space with registers for instrumentation, status, and control, as well as

EEPROM memory blocks to store parameters and user information. Byte addresses designated as “Reserved”

return undefined data when read. Reserved bytes should not be written. Several byte registers are paired into two-

byte registers in order to store 16-bit values. The most significant byte (MSB) of the 16 bit value is located at a

even address and the least significant byte (LSB) is located at the next address (odd) byte. When the MSB of a

two-byte register is read, the MSB and LSB are latched simultaneously and held for the duration of the read data

command to prevent updates to the LSB during the read. This ensures synchronization between the two register

bytes. For consistent results, always read the MSB and the LSB of a two-byte register during the same read data

command sequence.

EEPROM memory consists of the NV EEPROM cells overlaid with volatile shadow RAM. The Read Data and Write

Data commands allow the 2-Wire interface to directly accesses only the shadow RAM. The Copy Data and Recall

Data function commands transfer data between the shadow RAM and the EEPROM cells. In order to modify the

data stored in the EEPROM cells, data must be written to the shadow RAM and then copied to the EEPROM. In

order to verify the data stored in the EEPROM cells, the EEPROM data must be recalled to the shadow RAM and

then read from the shadow RAM. See Figure 23.

USER EEPROM

A 16 byte User EEPROM memory (block 0, addresses 20h - 2Fh) provides NV memory that is uncommitted to

other DS2782 functions. Accessing the User EEPROM block does not affect the operation of the DS2782. User

EEPROM is lockable, and once locked, write access is not allowed. The battery pack or host system manufacturer

can program lot codes, date codes and other manufacturing, warranty, or diagnostic information and then lock it to

safeguard the data. User EEPROM can also store parameters for charging to support different size batteries in a

host device as well as auxiliary model data such as time to full charge estimation parameters.

PARAMETER EEPROM

Model data for the cells, as well as application operating parameters are stored in the Parameter EEPROM

memory (block 1, addresses 60h - 7Fh). The ACR (MSB and LSB) and AS registers are automatically saved to

EEPROM when the RARC result crosses 4% boundaries. This allows the DS2782 to be located outside the

protection FETs. In this manner, if a protection device is triggered, the DS2782 cannot lose more that 4% of charge

or discharge data.

Figure 23. EEPROM Access via Shadow RAM

Serial

Interface

Write

Read

Shadow RAM

EEPROM

Copy

Recall

DS2782

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Table 2. Memory Map

ADDRESS (HEX) DESCRIPTION READ/WRITE

00 Reserved R

01 STATUS - Status Register R/W

02 RAAC - Remaining Active Absolute Capacity MSB R

03 RAAC - Remaining Active Absolute Capacity LSB R

04 RSAC - Remaining Standby Absolute Capacity MSB R

05 RSAC - Remaining Standby Absolute Capacity LSB R

06 RARC - Remaining Active Relative Capacity R

07 RSRC - Remaining Standby Relative Capacity R

08 IAVG - Average Current Register MSB R

09 IAVG - Average Current Register LSB R

0A TEMP - Temperature Register MSB R

0B TEMP - Temperature Register LSB R

0C VOLT - Voltage Register MSB R

0D VOLT - Voltage Register LSB R

0E CURRENT - Current Register MSB R

0F CURRENT - Current Register LSB R

10 ACR - Accumulated Current Register MSB R/W*

11 ACR - Accumulated Current Register LSB R/W*

12 ACRL - Low Accumulated Current Register MSB R

13 ACRL - Low Accumulated Current Register LSB R

14 AS - Age Scalar R/W*

15 SFR - Special Feature Register R/W

16 FULL - Full Capacity MSB R

17 FULL - Full Capacity LSB R

18 AE - Active Empty MSB R

19 AE - Active Empty LSB R

1A SE - Standby Empty MSB R

1B SE - Standby Empty LSB R

1C to 1E Reserved —

1F EEPROM - EEPROM Register R/W

20 to 2F User EEPROM, Lockable, Block 0 R/W

30 to 37 Additional User EEPROM, Lockable, Block 0 R/W

38 to 5F Reserved —

60 to 7F Parameter EEPROM, Lockable, Block 1 R/W

80 to EF Reserved —

F0 to F7 Unique ID R

80 to FF Reserved —

FE Function Command Register W

FF Reserved —

* Register value is automatically saved to EEPROM during ACTIVE mode operation and recalled from EEPROM on power up.

+ Unique 64 bit ID is a factory option available by special order. Units with IDs do not allow access to additional user EEPROM block 0.

DS2782

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Table 3. Parameter EEPROM Memory Block 1

ADDRESS

(HEX)

DESCRIPTION ADDRESS

(HEX)

DESCRIPTION

60 CONTROL - Control Register 70 AE 3040 Slope

61 AB - Accumulation Bias 71 AE 2030 Slope

62 AC - Aging Capacity MSB 72 AE 1020 Slope

63 AC - Aging Capacity LSB 73 AE 0010 Slope

64 VCHG - Charge Voltage 74 SE 3040 Slope

65 IMIN - Minimum Charge Current 75 SE 2030 Slope

66 VAE - Active Empty Voltage 76 SE 1020 Slope

67 IAE - Active Empty Current 77 SE 0010 Slope

68 Active Empty 40 78 RSGAIN - Sense Resistor Gain MSB

69 RSNSP - Sense Resistor Prime 79 RSGAIN - Sense Resistor Gain LSB

6A Full 40 MSB 7A RSTC - Sense Resistor Temp. Coeff.

6B Full 40 LSB 7B FRSGAIN - Factory Gain MSB

6C Full 3040 Slope 7C FRSGAIN - Factory Gain LSB

6D Full 2030 Slope 7D Reserved

6E Full 1020 Slope 7E 2-Wire Slave Address

6F Full 0010 Slope 7F Reserved

2-WIRE BUS SYSTEM

The 2-Wire bus system supports operation as a slave only device in a single or multi-slave, and single or multi-

master system. Up to 128 slave devices may share the bus by uniquely setting the 7-bit slave address. The 2-wire

interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and SCL provide bidirectional

communication between the DS2782 slave device and a master device at speeds up to 400 kHz. The DS2782’s

SDA pin operates bi-directionally, that is, when the DS2782 receives data, SDA operates as an input, and when the

DS2782 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up.

The DS2782 always operates as a slave device, receiving and transmitting data under the control of a master

device. The master initiates all transactions on the bus and generates the SCL signal as well as the START and

STOP bits which begin and end each transaction.

Bit Transfer

One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and

then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any

change in SDA when SCL is high is interpreted as a START or STOP control signal.

Bus Idle

The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high

when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.

START and STOP Conditions

The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL

is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL

is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one

transaction and begin another without returning the bus to the idle state. In multi-master systems, a Repeated

START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities

in which the SDA transitions when SCL is high.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

DS2782G+

Mfr. #:

Buy DS2782G+

Manufacturer:

Maxim Integrated

Description:

Battery Management Stand-Alone Fuel Gauge

Lifecycle:

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DS2782G+

DS2782G+

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