MAX5889EGK+TD Datasheet MAX5889EGK+D, MAX5889EGK+TD | P10-P12

MAX5889

Clock Inputs (CLKP, CLKN)

To achieve the best possible jitter performance, the

MAX5889 features flexible differential clock inputs

(CLKP, CLKN) that operate from a separate clock

power supply (AV

CLK

). Drive the differential clock

inputs from a single-ended or a differential clock

source. For highest dynamic performance, differential

clock source is required. For single-ended operation,

drive CLKP and bypass CLKN to CGND.

CLKP and CLKN are internally biased at AV

CLK

/ 2,

allowing the AC-coupling of clock sources directly to

the device without external resistors to define the DC

level. The input resistance from CLKP and CLKN to

ground is approximately 5kΩ.

Data-Timing Relationship

Figure 3 shows the timing relationship between digital

LVDS data, clock, and output signals. The MAX5889

features a 2ns hold, a -1.2ns setup, and a 2.5ns propa-

gation delay time. There is a 5.5 clock-cycle latency

between data write operation and the corresponding

analog output transition.

LVDS Data Inputs

The MAX5889 has 12 pairs of LVDS data inputs (offset

binary format) and can accept data rates up to

600MWps. Each differential input pair is terminated with

an internal 110Ω resistor. The common-mode input

resistance is 3.2kΩ.

Power-Down Operation (PD)

The MAX5889 features a power-down mode that

reduces the DAC’s power consumption. Set PD high to

power down the MAX5889. Set PD low or leave uncon-

nected for normal operation.

When powered down, the MAX5889 overall power con-

sumption is reduced to less than 13µW. The MAX5889

requires 350µs to wake up from power-down and enter

a fully operational state if the external reference is

used. If the internal reference is used, the power-down

recovery time is 10ms. The PD internal pulldown circuit

sets the MAX5889 in normal mode when PD is left

unconnected.

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

10 ______________________________________________________________________________________

OUT

OUTN OUTP

CURRENT

SOURCES

CURRENT

SWITCHES

DD3.3

Figure 2. Simplified Analog Output Structure

D0–D11

SETUP

HOLD

CLKP

CLKN

N + 2

N + 4

N + 6

IOUTP

IOUTN

N + 1

N + 3

N + 5

N + 7

OUT

N - 2

OUT

N - 3

OUT

N - 4

OUT

N - 5

OUT

N - 6

OUT

N - 7

OUT

N-1

OUT

Figure 3. Timing Relationship Between Clock, Input Data, and Analog Output

Applications Information

Clock Interface

To achieve the best possible jitter performance, the

MAX5889 features flexible differential clock inputs

(CLKP, CLKN) that operate from a separate clock

power supply (AV

CLK

). Use a low-jitter clock to reduce

the DAC’s phase noise and wideband noise. To

achieve the best DAC dynamic performance, the

CLKP/CLKN input source must be designed carefully.

The differential clock (CLKN and CLKP) input can be

driven from a single-ended or a differential clock

source. Use differential clock drive to achieve the best

dynamic performance from the DAC. For single-ended

operation, drive CLKP with a low-noise source and

bypass CLKN to CGND with a 0.1µF capacitor.

Figure 4 shows a convenient and quick way of applying

a differential signal created from a single-ended source

using a wideband transformer. Alternatively, drive

CLKP/CLKN from a CMOS-compatible clock source.

Use sine wave or AC-coupled differential ECL/PECL

drive for best dynamic performance.

Differential Output Coupling Using a

Wideband RF Transformer

Use a pair of transformers (Figure 5) or a differential

amplifier configuration to convert the differential voltage

existing between OUTP and OUTN to a single-ended

voltage. Optimize the dynamic performance by using a

differential transformer-coupled output and limit the out-

put power to <0dBm full scale. To achieve the best

dynamic performance, use the differential transformer

configuration. Terminate the DAC as shown in Figure 5,

and use 50Ω termination at the transformer single-

ended output. This provides double 50Ω termination for

the DAC output network. With the double-terminated

output and 20mA full-scale current, the DAC produces a

full-scale signal level of approximately -2dBm. Pay close

attention to the transformer core saturation characteris-

tics when selecting a transformer for the MAX5889.

Transformer core saturation can introduce strong 2nd-

order harmonic distortion especially at low output fre-

quencies and high signal amplitudes. For best results,

connect the center tap of the transformer to ground.

When not using a transformer, terminate each DAC out-

put to ground with a 25Ω resistor. Additionally, place a

50Ω resistor between the outputs (Figure 6).

For a single-ended unipolar output, select OUTP as the

output and connect OUTN to AGND. Operating the

MAX5889 single-ended is not recommended because

it degrades the dynamic performance.

The distortion performance of the DAC depends on the

load impedance. The MAX5889 is optimized for 50Ω

differential double termination. Using higher termination

impedance degrades distortion performance and

increases output noise voltage.

MAX5889

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

______________________________________________________________________________________ 11

WIDEBAND RF TRANSFORMER

PERFORMS SINGLE-ENDED-TO-

DIFFERENTIAL CONVERSION

SINGLE-ENDED

CLOCK SOURCE

AGND

1:1

25Ω

CLKP

CLKN

TO DAC

0.1µF

Figure 4. Differential Clock-Signal Generation

MAX5889

OUTP

OUTN

WIDEBAND RF TRANSFORMER T2 PERFORMS THE

DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION

T1, 1:1

T2, 1:1

AGND

50Ω

100Ω

50Ω

OUT

, SINGLE-ENDED

D0–D11

LVDS

DATA INPUTS

Figure 5. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer

MAX5889

Grounding, Bypassing, and Power-Supply

Considerations

Grounding and power-supply decoupling strongly influ-

ence the MAX5889 performance. Unwanted digital

crosstalk coupling through the input, reference, power

supply, and ground connections affects dynamic per-

formance. High-speed, high-frequency applications

require closely followed proper grounding and power-

supply decoupling. These techniques reduce EMI and

internal crosstalk that can significantly affect the

MAX5889 dynamic performance.

Use a multilayer printed circuit (PC) board with sepa-

rate ground and power-supply planes. Run high-speed

signals on lines directly above the ground plane. Keep

digital signals as far away from sensitive analog inputs

and outputs, reference input sense lines, common-

mode inputs, and clock inputs as practical. Use a sym-

metric design of clock input and the analog output lines

to minimize 2nd-order harmonic distortion components,

thus optimizing the DAC’s dynamic performance. Keep

digital signal paths short and run lengths matched to

avoid propagation delay and data skew mismatches.

The MAX5889 requires five separate power-supply

inputs for analog (AV

DD1.8

and AV

DD3.3

), digital

(DV

DD1.8

and DV

DD3.3

), and clock (AV

CLK

) circuitry.

Decouple each AV

DD3.3

, AV

DD1.8

, AV

CLK

, DV

DD3.3

, and

DD1.8

input with a separate 0.1µF capacitor as close

to the device as possible with the shortest possible con-

nection to the respective ground plane (Figure 7).

Connect all the 3.3V supplies together at one point with

ferrite beads to minimize supply noise coupling.

Decouple all five power-supply voltages at the point they

enter the PC board with tantalum or electrolytic capaci-

tors. Ferrite beads with additional decoupling capacitors

forming a pi network can also improve performance.

Similarly, connect all 1.8V supplies together at one point

with ferrite beads.

The analog and digital power-supply inputs AV

DD3.3

CLK

, and DV

DD3.3

allow a 3.135V to 3.465V supply

voltage range. The analog and digital power-supply

inputs AV

DD1.8

and DV

DD1.8

allow a 1.71V to 1.89V

supply voltage range.

The MAX5889 is packaged in a 68-pin QFN-EP pack-

age with exposed paddle, providing optimized DAC AC

performance. The exposed pad must be soldered to

the ground plane of the PC board. Thermal efficiency is

not the key factor, since the MAX5889 features low-

power operation. The exposed pad ensures a solid

ground connection between the DAC and the PC

board’s ground layer.

The data converter die attaches to an EP lead frame

with the back of this frame exposed at the package

bottom surface, facing the PC board side of the pack-

age. This allows for a solid attachment of the package

to the PC board with standard infrared (IR) reflow sol-

dering techniques. A specially created land pattern on

the PC board, matching the size of the EP (6mm x

6mm), ensures the proper attachment and grounding of

the DAC. Place vias into the land area and implement

12-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

12 ______________________________________________________________________________________

MAX5889

OUTP

OUTN

AGND

25Ω

50Ω

25Ω

OUTP

OUTN

D0–D11

LVDS

DATA INPUTS

Figure 6. Differential Output Configuration

MAX5889

OUTPAV

DD3.3

DD1.8

DD3.3

DD1.8

CLK

OUTN

0.1

3.3V VOLTAGE SUPPLY

0.1

F 0.1

1.8V VOLTAGE SUPPLY

0.1

BYPASSING—DAC LEVEL

*FERRITE BEADS

D0–D11

LVDS

DATA INPUTS

Figure 7. Recommended Power-Supply Decoupling and

Bypassing Circuitry

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX5889EGK+TD

Mfr. #:

Buy MAX5889EGK+TD

Manufacturer:

Maxim Integrated

Description:

Digital to Analog Converters - DAC 12-Bit 600Msps DAC

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MAX5889EGK+TD

MAX5889EGK+TD

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