large ground planes in the PC board design to ensure
the highest dynamic performance of the DAC. Connect
the MAX5889 exposed paddle to the common connec-
tion point of DGND, AGND, and CGND. Vias connect
the top land pattern to internal or external copper
planes. Use as many vias as possible to the ground
plane to minimize inductance. The vias should have a
diameter greater than 0.3mm.
Static Performance Parameter
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a line drawn between the
end points of the transfer function, once offset and gain
errors have been nullified. For a DAC, the deviations
are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impulse
is usually specified in pV
s.
Dynamic Performance Parameter
Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of the
full-scale analog output (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical maxi-
mum can be derived from the DAC’s resolution (N bits):
SNR = 6.02 x N + 1.76
However, noise sources such as thermal noise, refer-
ence noise, clock jitter, etc., affect the ideal reading;
therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantiza-
tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR is
usually measured in dBc and with respect to the carrier
frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or to
Nyquist.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order IMD differential product to
either output tone. The two-tone IMD performance of
the MAX5889 is tested with the two individual output
tone levels set to at least -6.5dBFS.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (WCDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
______________________________________________________________________________________ 13
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
14 ______________________________________________________________________________________
Pin Configuration
D0N
1
N.C.
2
N.C.
3
N.C.
4
N.C.
5
N.C.
6
N.C.
7
N.C.
8
N.C.
9
DGND
10
DV
DD3.3
11
PD
12
N.C.
13
AV
DD3.3
14
AGND
15
REFIO
EXPOSED PADDLE
16
FSADJ
17
D8P
51
D9N
50
D9P
49
D10N
48
D10P
47
D11N
46
D11P
45
N.C.
44
N.C.
43
N.C.
42
AV
CLK
41
CGND
40
CLKP
39
CLKN
38
CGND
37
AV
CLK
36
AV
DD1.8
35
DACREF
18
AV
DD1.819
AGND
20
AV
DD3.321
AV
DD3.322
AGND
23
AGND
24
AV
DD3.325
AV
DD3.326
AGND
27
OUTN
28
OUTP
29
AGND
30
AV
DD3.331
AV
DD3.332
AGND
33
AV
DD1.834
D0P
68
D1N
67
D1P
66
D2N
65
D2P
64
D3N
63
D3P
62
DV
DD1.8
61
D4N
60
D4P
59
D5N
58
D5P
57
D6N
56
D6P
55
D7N
54
D7P
53
D8N
52
MAX5889
QFN-EP
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
______________________________________________________________________________________ 15
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM

MAX5889EGK+TD

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 600Msps DAC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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