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MAX5889EGK+TD

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥ +25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Glitch Impulse Measured differentially 1
pV•s
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Input Data Rate 600
MWps
Data Latency 5.5
Clock
cycles
Data to Clock Setup Time t
SETUP
Referenced to rising edge of clock (Note 4) -1.5
ns
Data to Clock Hold Time t
HOLD
Referenced to rising edge of clock (Note 4)
2.6 ns
Clock Frequency f
CLK
CLKP, CLKN 600
MHz
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN 0.6 ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN 0.6 ns
Turn-On Time t
SHDN
External reference, PD falling edge to
output settle within 1%
350
µs
CMOS LOGIC INPUT (PD)
Input Logic High V
IH
0.7 x
DV
DD3.3
V
Input Logic Low V
IL
0.3 x
DV
DD3.3
V
Input Current I
IN
-10
±1.8 +10
µA
Input Capacitance C
IN
3pF
LVDS INPUTS
Differential Input High
V
IHLVDS
(Notes 6, 7, 8)
+100 +1000
mV
Differential Input Low
V
ILLVDS
(Notes 6, 7, 8)
-1000 -100
mV
Internal Common-Mode Bias
V
ICMLVDS
1.125 1.375
V
Differential Input Resistance
R
IDLVDS
110
Ω
Common-Mode Input Resistance
R
ICMLVDS
3.2 kΩ
Input Capacitance
C
INLVDS
3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
Clock Common-Mode Voltage CLKP and CLKN are internally biased
AV
CLK
/ 2
V
Minimum Differential Input
Voltage Swing
0.5
V
P-P
Minimum Common-Mode Voltage
1V
Maximum Common-Mode
Voltage
1.9 V
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
_______________________________________________________________________________________ 5
Note 2: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5889.
Note 3: Parameter measured single-ended with 50Ω double-terminated outputs.
Note 4: Not production tested. Guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
Note 6: Not production tested. Guaranteed by design.
Note 7: Differential input voltage defined as V
D_P
- V
D_N
.
Note 8: Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥ +25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Resistance R
CLK
Single-ended 5 kΩ
Input Capacitance C
CLK
3pF
POWER SUPPLIES
AV
DD3.3
3.135
3.3
3.465
Analog Supply Voltage Range
AV
DD1.8
1.710
1.8
1.890
V
Clock Supply Voltage Range AV
CLK
3.135
3.3
3.465
V
DV
DD3.3
3.135
3.3
3.465
Digital Supply Voltage Range
DV
DD1.8
1.710
1.8
1.890
V
f
CLK
= 100MHz, f
OUT
= 16MHz
26.5
f
CLK
= 500MHz, f
OUT
= 16MHz
26.5 28.5I
AVDD3.3
f
CLK
= 600MHz, f
OUT
= 16MHz
26.5
f
CLK
= 100MHz, f
OUT
= 16MHz
11.3
f
CLK
= 500MHz, f
OUT
= 16MHz 50 58
Analog Supply Current
I
AVDD1.8
f
CLK
= 600MHz, f
OUT
= 16MHz 60
mA
f
CLK
= 100MHz, f
OUT
= 16MHz 2.8
f
CLK
= 500MHz, f
OUT
= 16MHz 2.8 3.6Clock Supply Current I
AVCLK
f
CLK
= 600MHz, f
OUT
= 16MHz 2.8
mA
f
CLK
= 100MHz, f
OUT
= 16MHz 0.2
f
CLK
= 500MHz, f
OUT
= 16MHz 0.2 0.5
I
DVDD3.3
f
CLK
= 600MHz, f
OUT
= 16MHz 0.2
f
CLK
= 100MHz, f
OUT
= 16MHz
10.2
f
CLK
= 500MHz, f
OUT
= 16MHz 42 48
Digital Supply Current
I
DVDD1.8
f
CLK
= 600MHz, f
OUT
= 16MHz 48
mA
f
CLK
= 100MHz, f
OUT
= 16MHz
137
f
CLK
= 500MHz, f
OUT
= 16MHz
263
297
f
CLK
= 600MHz, f
OUT
= 16MHz
292
mW
Total Power Dissipation P
DISS
Power-down, clock static low,
data input static
13 µW
Power-Supply Rejection Ratio PSRR (Note 5)
±0.025
%FS
V
D_N
V
D_P
V
IHLVDS
V
ILLVDS
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-termi-
nated, transformer-coupled output, I
OUT
= 20mA, T
A
= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5889 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
302010
10
20
30
40
50
60
70
80
90
100
0
05040
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5889 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
706040 5020 3010
10
20
30
40
50
60
70
80
90
100
0
080
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 500MHz)
MAX5889 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
10
20
30
40
50
60
70
80
90
100
0
0200
-6dBFS
-12dBFS
0dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 600MHz)
MAX5889 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
10
20
30
40
50
60
70
80
90
100
0
0 200
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(f
CLK
= 500MHz, I
OUT
= 20mA, 10mA, 5mA)
MAX5889 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1601208040
10
20
30
40
50
60
70
80
90
100
0
0200
20mA
10mA
5mA
0dBFS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX5889EGK+TD

Mfr. #:
Buy MAX5889EGK+TD
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 600Msps DAC
Lifecycle:
New from this manufacturer.
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