25
LTC4230
4230f
4
3
21
+
V
CC
n
RESET
n
SENSE
n
ON
R5
15k
LTC4230*
GATE
n
FB
n
4230 F14a
15
14
12
C
TIMER
1µF
GND
TIMER
RESET
R4
36k
V
OUT
5V
5A
Q1
Si4410DY
R
SENSE
0.007Ω
C
OUT
R6
10k
Z1**
Z1: SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**OPTIONAL
R1
10Ω
C1
0.1µF
R2
10k
V
IN
5V
SHORT
LONG
V
CC
RESET
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
4
3
21
+
V
CC
n
SENSE
n
ON
R2
100k
RESET
LTC4230*
GATE
n
FB
n
4230 F14b
15
14
12
C
TIMER
1µF
R3
10k
GND
TIMER
RESET
n
V
OUT
5V
5A
Q1
Si4410DY
R
SENSE
0.007Ω
C
OUT
R1
36k
R4
10k
R5
10k
PCB
CONNECTION
SENSE
R
X
10Ω
C
X
0.1µF
Z1**
V
CC
5V
SHORT
LONG
SHORT
PCB EDGE
CONNECTOR
(MALE)
LONG
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
Q2
R7
15k
Z1: SMAJ10
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**OPTIONAL
(14a) Hot Swap Controller On Daughter Board
(14b) Hot Swap Controller on Backplane
Figure 14. Staggered Pin Connections
PCB CONNECTION SENSE
There are a number of ways to use the LTC4230’s ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4230 commences
a start-up cycle.
The first example is shown in the schematic on the front
page of this data sheet. In this case, the LTC4230 is
mounted on the PCB and a 10k resistive divider is con-
nected to the ON pin. On the edge connector, R1 is wired
to a short pin. Until the connectors are fully mated, the ON
pin is held low, keeping the LTC4230 in an OFF state. Once
the connectors are mated, the resistive divider is
con
nected to V
CC1
, V
ON
> 1.314V and the LTC4230 begins
a start-up cycle.
In Figure 14a, an LTC4230 is illustrated in a basic configu-
ration on a PCB daughter card. The ON pin is connected
directly to V
CC
on the backplane once the card is seated
into the backplane. R2 is provided to bleed off any potential
static charge which might exist on the backplane, the
connector or during card installation.
A third example is shown in Figure 14b where the LTC4230
is mounted on the backplane. In this example, a 2N2222
transistor and a pair of resistors (R4, R5) form the PCB
connection sense circuit. With the card out of the chassis,
Q2’s base is biased to V
CC
through R5, biasing Q2 on and
driving the LTC4230’s ON pin low. The base of Q2 is also
wired to a socket on the backplane connector. When a card
is firmly seated into the backplane, the base of Q2 is then
grounded through a short pin connection on the card. Q2
is biased off, the LTC4230’s ON pin is pulled-up to V
CC
and
a start-up cycle begins.
APPLICATIO S I FOR ATIO
WUU
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