31
LTC4230
4230f
APPLICATIO S I FOR ATIO
WUU
U
bias current 1N4691 zener diode is chosen to protect the
system. Here, the zener diode is connected from V
CC
to
the LTC4230’s FILTER pin. If the input voltage to the
system is greater than 6.8V during start-up, the voltage
on the FILTER pin is pulled higher than its 1.19V thresh-
old. As a result, the GATE
n
pin is not allowed to ramp and
the second timing cycle will not commence until the
supply overvoltage condition is removed. Should the
supply overvoltage condition occur during normal op-
eration, internal control logic would trip the electronic
circuit breaker and the GATE would be pulled to ground,
shutting off the external pass transistor. If a lower supply
overvoltage threshold is desired, use a zener diode with
a smaller breakdown voltage.
A timing diagram for illustrating LTC4230 operation under
a high side overvoltage condition is shown in Figure 23.
The start-up sequence in this case (between Time Points
1 and 2) is identical to any other start-up sequence under
normal operating conditions. At Time Point 2, the input
supply voltage causes the zener diode to conduct thereby
forcing V
FILTER
> 1.19V. At Time Point 3, FAULT is asserted
low and the TIMER pin voltage ramps down. At Time
Point␣ 4, the LTC4230 checks if V
FILTER
< 1.19V. FAULT is
asserted low (but not latched) to indicate a start-up failure.
Only if the input overvoltage condition is removed before
Time Point 5 does the start-up sequence resume at the
second timing cycle. At this point in time, the GATE
n
pin
voltage is allowed to ramp up, FAULT is pulled to logic high
and the circuit breaker is armed. Should, at any time after
Time Point 5, a supply overvoltage condition develop
(V
FILTER
> 1.26V), the electronic circuit breaker will trip,
the GATE
n
will be pulled low to turn off the external
MOSFET and FAULT will be asserted low and latched.
Low Side (Output) Overvoltage Protection
A zener diode can be used in a similar fashion to detect/
protect the system against a supply overvoltage condition
on the load (or low) side of the pass transistor. In this case,
the zener diode is connected from the load to the LTC4230’s
FILTER pin, as shown in Figure 24. An additional diode,
D1, prevents the FILTER pin from pulling low during
output short-circuit. Figure 25 illustrates the timing dia-
gram for a low side output overvoltage condition. In this
example, the LTC4230 can only sense the overvoltage
supply condition after Time Point 5 and the GATE
n
pin has
ramped up to its nominal operating value. After Time
Point␣ 5, a supply voltage fault occurs at the load and the
zener diode conducts, causing V
FILTER
to increase. At Time
Point 6, V
FILTER
is greater than 1.26V, the circuit breaker
trips, GATE pulls to ground and FAULT asserts low and is
latched.
In either case, the LTC4230 can be configured to auto-
matically initiate a start-up sequence. Please refer to the
section on AutoRetry After a Fault for additional
information.
PCB LAYOUT CONSIDERATIONS
For proper operation of the LTC4230’s circuit breaker
function, a 4-wire Kelvin connection to the sense resistors
is highly recommended. A recommended PCB layout for
the sense resistor, the power MOSFET and the GATE drive
components around the LTC4230 is illustrated in Fig-
ure␣ 26. In Hot Swap applications where load currents can
reach 10A or more, narrow PCB tracks exhibit more
resistance than wider tracks and operate at more elevated
temperatures. Since the sheet resistance of 1 ounce
copper foil is approximately 0.54m/square, track resis-
tances add up quickly in high current applications. Thus,
to keep PCB track resistance and temperature rise to a
minimum, PCB track width must be appropriately sized.
Consult Appendix A of LTC Application Note 69 for details
on sizing and calculating trace resistances as a function of
copper thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
32
LTC4230
4230f
Figure 23. High Side Overvoltage Protection Timing
1 3 7654
4230 F23
FAULT IS PULLED LOW (BUT NOT LATCHED), SINCE THE
OVERVOLTAGE HAPPENED BEFORE THE END OF THE FIRST TIMING CYCLE
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
+ 50mV)
2
FAST COMPARATOR
ARMED
IF THE OVERVOLTAGE GOES AWAY,
THE SECOND CYCLE CONTINUES
SLOW COMPARATOR
ARMED
FILTER < 1.19V
ON
TIMER
GATE
n
V
OUT
n
FILTER
FAULT
RESET
GATE
n
V
OUT
n
CHECK FOR
GATE
n
< 0.25V
POWER GOOD
APPLICATIO S I FOR ATIO
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33
LTC4230
4230f
Figure 24. LTC4230 Low Side Overvoltage Protection Implementation
APPLICATIO S I FOR ATIO
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LONG
LONG
LONG
SHORT
LONG
SHORT
10k
R
SENSE2
0.007
CX2
100nF
CX1
100nF
RX2
10
M2
IRF7413
V
CC1
GND
ON
FAULT
LTC4230
14
FB3
1
15
13
SENSE 1 GATE 1
FILTER TIMER
V
CC2
SENSE 2 GATE 2 SENSE 3 GATE 3V
CC3
RESET 3
2
R
SENSE3
0.007
RX1
10
R8
5.1k
R9
12k
M3
IRF7413
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
V
OUT3
1.8V
5A
R
SENSE1
0.007
CX3
100nF
RX3
10
C
FILTER
15pF
C
TIMER
0.1µF
R4
10k
OPTIONAL
V
CC1
10k
V
CC1
R5
10k
M4
V
CC1
M1
IRF7413
Z3
V
OUT1
Z2
Z1
RESET 2
19
FB2
20
R7
10k
RESET 1
9
FB1
10
R10
11k
R11
12k
R6
10k
R12
18k
R13
12k
4230 F24
R5
10k
µP OR
SYSTEM LOGIC
MASTER
RESET
3-INPUT
NOR GATE
67 816171854 3
1211
D1: 1N4148
M4: 2N7002LT1
Z1, Z2, Z3: SMAJ10
Z4, Z5, Z6: 1N4691
NOTE: FOR ANY V
OUT
n
> 8.4V, THE
LTC4230 IS IN OVERVOLTAGE
PROTECTION MODE, FAULT IS PULLED LOW
C
OUT3
C
OUT2
C
OUT1
V
OUT2
V
OUT3
6.2V
Z4 Z5 Z6
D1
+
+
+
PCB EDGE
CONNECTOR
(MALE)
BACKPLANE
CONNECTOR
(FEMALE)
V
CC1
3.3V
V
CC2
2.5V
V
CC3
1.8V
ON/OFF
FAULT
GND

LTC4230CGN

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Hot Swap Voltage Controllers LTC4230 - Triple Hot Swap Controller with Multifunction Current Control
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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