AT49BV6416-70TU Datasheet AT49BV6416-70TI, AT49BV6416-70TU, AT49BV6416-70TI-T | P1-P3

Features

•

64-megabit (4M x 16) Flash Memory

•

2.7V - 3.6V Read/Write

•

High Performance

– Asynchronous Access Time – 70 ns

– Page Mode Read Time – 20 ns

•

Sector Erase Architecture

– Eight 4K Word Sectors with Individual Write Lockout

– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout

•

Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms

•

Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being

Programmed/Erased

– Memory Plane A: 16M of Memory Including Eight 4K Word Sectors

– Memory Plane B: 16M of Memory Consisting of 32K Word Sectors

– Memory Plane C: 16M of Memory Consisting of 32K Word Sectors

– Memory Plane D: 16M of Memory Consisting of 32K Word Sectors

•

Suspend/Resume Feature for Erase and Program

– Supports Reading and Programming Data from Any Sector by Suspending Erase

of a Different Sector

– Supports Reading Any Word by Suspending Programming of Any Other Word

•

Low-power Operation

– 30 mA Active

– 35 µA Standby

•

2.2V I/O Option Reduces Overall System Power

•

Data Polling and Toggle Bit for End of Program Detection

•

VPP Pin for Write Protection and Accelerated Program Operations

•

RESET Input for Device Initialization

•

TSOP Package

•

Top or Bottom Boot Block Configuration Available

•

128-bit Protection Register

•

Common Flash Interface (CFI)

•

Green (Pb/Halide-free) Packaging Option

1. Description

The AT49BV6416(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided

into multiple sectors and planes for erase operations. The device can be read or

reprogrammed off a single 2.7V power supply, making it ideally suited for in-system

programming. The output voltage can be separately controlled down to 2.2V through

the VCCQ supply pin. The device can operate in the asynchronous or page read

mode.

The AT49BV6416(T) is divided into four memory planes. A read operation can occur

in any of the three planes which is not being programmed or erased. This concurrent

operation allows improved system performance by not requiring the system to wait for

a program or erase operation to complete before a read is performed. To further

increase the flexibility of the device, it contains an Erase Suspend and Program Sus-

pend feature. This feature will put the erase or program on hold for any amount of time

and let the user read data from or program data to any of the remaining sectors. There

is no reason to suspend the erase or program operation if the data to be read is in

another memory plane. The end of program or erase is detected by Data

Polling or

toggle bit.

64-megabit

(4M x 16)

Page Mode

2.7-volt Flash

Memory

AT49BV6416

AT49BV6416T

Not Recommended

for New Design. Use

AT49BV642D(T).

3451D–FLASH–04/06

AT49BV6416(T)

The VPP pin provides data protection and faster programming times. When the V

input is

below 0.7V, the program and erase functions are inhibited. When V

is at 1.65V or above, nor-

mal program and erase operations can be performed. With V

at 10.0V, the program (dual-

word program command) operation is accelerated.

A six-byte command (Enter Single Pulse Program Mode) to remove the requirement of entering

the three-byte program sequence is offered to further improve programming time. After entering

the six-byte code, only single pulses on the write control lines are required for writing into the

device. This mode (Single Pulse Word Program) is exited by powering down the device, by tak-

ing the RESET

pin to GND or by a high-to-low transition on the V

input. Erase, Erase

Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in

this mode; if entered they will result in data being programmed into the device. It is not recom-

mended that the six-byte code reside in the software of the final product but only exist in external

programming code.

2. Pin Configurations

2.1 TSOP Top View (Type 1)

Pin Name Pin Function

I/O0 - I/O15 Data Inputs/Outputs

A0 - A21 Addresses

Chip Enable

Output Enable

Write Enable

RESET

Reset

Write Protect

VPP

Write Protection and Power Supply for Accelerated Program

Operations

VCCQ Output Power Supply

A15

A14

A13

A12

A11

A10

A21

A20

RESET

VPP

A19

A18

A17

A16

VCCQ

GND

I/O15

I/O7

I/O14

I/O6

I/O13

I/O5

I/O12

I/O4

VCC

I/O11

I/O3

I/O10

I/O2

I/O9

I/O1

I/O8

I/O0

GND

3451D–FLASH–04/06

AT49BV6416(T)

3. Device Operation

3.1 Command Sequences

The device powers on in the read mode. Command sequences are used to place the device in

other operating modes such as program and erase. After the completion of a program or an

erase cycle, the device enters the read mode. The command sequences are written by applying

a low pulse on the WE

input with CE low and OE high or by applying a low-going pulse on the

input with WE low and OE high. The address is latched on the falling edge of the WE or CE

pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse,

whichever occurs first. The addresses used in the command sequences are not affected by

entering the command sequences.

3.2 Asynchronous Read

The AT49BV6416(T) is accessed like an EPROM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins are asserted on the outputs.

The outputs are put in the high impedance state whenever CE

or OE is high. This dual-line con-

trol gives designers flexibility in preventing bus contention.

3.3 Page Read

The page read operation of the device is controlled by CE and OE inputs. The page size is four

words. The first word access of the page read is the same as the asynchronous read. The first

word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1

will result in subsequent reads within the page being output at a speed of 20 ns. The “Page

Read Cycle Waveform” is shown on page 21.

3.4 Reset

A RESET input pin is provided to ease some system applications. When RESET is at a logic

high level, the device is in its standard operating mode. A low level on the RESET

pin halts the

present device operation and puts the outputs of the device in a high-impedance state. When a

high level is reasserted on the RESET

pin, the device returns to read or standby mode, depend-

ing upon the state of the control pins.

3.5 Erase

Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a

logical “1”. The entire memory can be erased by using the Chip Erase command or individual

planes or sectors can be erased by using the Plane Erase or Sector Erase commands.

3.5.1 Chip Erase

Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the

last WE

pulse. Chip Erase does not alter the data of the protected sectors. After the full chip

erase the device will return back to the read mode. The hardware reset during Chip Erase will

stop the erase but the data will be of unknown state. Any command during Chip Erase except

Erase Suspend will be ignored.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

AT49BV6416-70TU

Mfr. #:

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IC FLASH 64M PARALLEL 48TSOP

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AT49BV6416-70TU

AT49BV6416-70TU

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