20
3451D–FLASH–04/06
AT49BV6416(T)
17. Asynchronous Read Cycle Waveform
(1)(2)(3)
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE
may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE, whichever occurs first (CL = 5 pF).
16. AC Asynchronous Read Timing Characteristics
Symbol Parameter Min Max Units
t
RC
Read Cycle Time 70 ns
t
ACC
Access, Address to Data Valid 70 ns
t
CE
Access, CE to Data Valid 70 ns
t
OE
OE to Data Valid 20 ns
t
DF
CE, OE High to Data Float 25 ns
t
OH
Output Hold from OE, CE or Address, whichever Occurs First 0 ns
t
RO
RESET to Output Delay 150 ns
OUTPUT
VALID
I/O0 - I/O15
HIGH Z
RESET
OE
t
OE
t
CE
ADDRESS VALID
t
DF
t
OH
t
ACC
t
RO
CE
A0 - A21
t
RC
