10
3451D–FLASH–04/06
AT49BV6416(T)
Figure 3-4. Toggle Bit Algorithm
(Configuration Register = 00)
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
NO
NO
NO
YES
YES
YES
Figure 3-5. Toggle Bit Algorithm
(Configuration Register = 01)
Note: 1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
Toggle?
I/O3, I/O5 = 1?
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
NO
NO
NO
YES
YES
YES
11
3451D–FLASH–04/06
AT49BV6416(T)
4. Status Bit Table
I/O7 I/O6 I/O2
Configuration
Register: 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01 00/01
Read Address
In
Plane A Plane B Plane C Plane D Plane A Plane B Plane C Plane D Plane A Plane B Plane C Plane D
While
Programming
in Plane A
I/O7
/ 0 DATA DATA DATA TOG G LE DATA DATA DATA 1 DATA DATA DATA
Programming
in Plane B
DATA I/O7
/ 0 DATA DATA DATA TO GGL E DATA DATA DATA 1 DATA DATA
Programming
in Plane C
DATA DATA I/O7
/ 0 DATA DATA DATA TO GGL E DATA DATA DATA 1 DATA
Programming
in Plane D
DATA DATA DATA I/O7
/0 DATA DATA DATA TOGGLE DATA DATA DATA 1
Erasing in
Plane A
0 / 0 DATA DATA DATA TO GG L E DATA DATA DATA TOG GLE DATA DATA DATA
Erasing in
Plane B
DATA 0/ 0 DATA DATA DATA TO GGL E D ATA DATA DATA TO GG L E DATA DATA
Erasing in
Plane C
DATA DATA 0 /0 DATA DATA DATA TO GGL E DATA DATA DATA TOG GLE D ATA
Erasing in
Plane D
DATA DATA DATA 0/ 0 DATA DATA DATA TOG GLE DATA DATA DATA TOG GL E
Erase
Suspended &
Read Erasing
Sector
1111 1111TOGGLETOGGLETOGGLETOGGLE
Erase
Suspended &
Read Non-
erasing Sector
DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
Erase
Suspended &
Program Non-
erasing Sector
in Plane A
I/O7
/ 0 DATA DATA DATA TO GG LE D ATA DATA DATA TO G G L E DATA DATA DATA
Erase
Suspended &
Program Non-
erasing Sector
in Plane B
DATA I/O7
/ 0 DATA DATA DATA TOG G L E DATA DATA DATA TOG G L E DATA DATA
Erase
Suspended &
Program Non-
erasing Sector
in Plane C
DATA DATA I/O7/ 0 DATA DATA DATA TO GG LE DATA DATA DATA TOG GL E DATA
Erase
Suspended &
Program Non-
erasing Sector
in Plane D
DATA DATA DATA I/O7
/0 DATA DATA DATA TOGGLE DATA DATA DATA TOGGLE
Erase
Suspended &
Program
Suspended &
Read from
Non-
suspended
Sectors
DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
12
3451D–FLASH–04/06
AT49BV6416(T)
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in
each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 14 - 17
for details).
5. Once a sector is in the Hardlock protection mode, it cannot be disabled unless the chip is reset or power cycled.
6. PA is the plane address (A21 - A20).
7. During the fourth bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address
PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H. PA (A21 - A20) must spec-
ify the same plane address as specified in the third bus cycle.
8. The fast programming option enables the user to program two words in parallel only when V
PP
= 10V. The addresses, Addr0
and Addr1, of the two words, D
IN0
and D
IN1
, must only differ in address A0. This command should be used for manufacturing
purpose only.
9. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
10. The default state (after power-up) of the configuration register is “00”.
11. Any address within the user programmable register region. Please see “Protection Register Addressing Table” on page 13.
12. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 3F80H.
13. For the AT49BV6416, xxxx = 0000H. For the AT49BV6416T, xxxx = 0F80H.
5. Command Definition Table
Command Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr D
OUT
Chip Erase 6 555 AA AAA
(2)
55 555 80 555 AA AAA 55 555 10
Plane Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 PA
(6)
20
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
(4)
30
Word Program 4 555 AA AAA 55 555 A0 Addr D
IN
Dual-Word Program
(8)
5 555 AA AAA 55 555 A1 Addr0 D
IN0
Addr1 D
IN1
Enter Single-pulse Program
Mode
6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0
Single-pulse Word Program
Mode
1 Addr D
IN
Sector Softlock 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
(4)
40
Sector Unlock 2 555 AA SA
(4)
70
Sector Hardlock 6 555 AA AAA 55 555 80 555 AA AAA 55 SA
(4)(5)
60
Erase/Program Suspend 1 xxx B0
Erase/Program Resume 1 PA
(6)
30
Product ID Entry
(7)
3 555 AA AAA 55 PA+00555 90
Product ID Exit
(3)
3 555 AA AAA 55 555 F0
Product ID Exit
(3)
1xxxFX
Program Protection
Register – Block B
4 555 AA AAA 55 555 C0 xxxx
(12)
8x
(11)
D
IN
Lock Protection
Register – Block B
4 555 AA AAA 55 555 C0 xxxx80
(12)
X0
Status of Block B
Protection
4 555 AA AAA 55 555 90 xxxx80
(13)
D
OUT
(9)
Set Configuration Register 4 555 AA AAA 55 555 E0 xxx 00/01
(10)
CFI Query 1 X55 98

AT49BV6416-70TU

Mfr. #:
Manufacturer:
Description:
IC FLASH 64M PARALLEL 48TSOP
Lifecycle:
New from this manufacturer.
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