AT49BV6416-70TU Datasheet AT49BV6416-70TI, AT49BV6416-70TU, AT49BV6416-70TI-T | P7-P9

3451D–FLASH–04/06

AT49BV6416(T)

The toggle bit status bit should be used in conjunction with the erase/program and V

status bit

as shown in the algorithm in Figures 3-4 and 3-5 on page 10.

3.8.3 Erase/Program Status Bit

The device offers a status bit on I/O5 that indicates whether the program or erase operation has

exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to

verify that an erase or a word program operation has been successfully performed. The device

may also output a “1” on I/O5 if the system tries to program a “1” to a location that was previ-

ously programmed to a “0”. Only an erase operation can change a “0” back to a “1”. If a program

(Sector Erase) command is issued to a protected sector, the protected sector will not be pro-

grammed (erased). The device will go to a status read mode and the I/O5 status bit will be set

high, indicating the program (erase) operation did not complete as requested. Once the

erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-

mand to return to the read mode. The erase/program status bit is a “0” while the erase or

program operation is still in progress. Please see “Status Bit Table” on page 11 for more details.

3.8.4 VPP Status Bit

The AT49BV6416(T) provides a status bit on I/O3 that provides information regarding the volt-

age level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is

not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”.

Once the V

status bit has been set to a “1”, the system must write the Product ID Exit com-

mand to return to the read mode. On the other hand, if the voltage level is high enough to

perform a program or erase operation successfully, the V

status bit will output a “0”. Please

see “Status Bit Table” on page 11 for more details.

3.9 Erase Suspend/Erase Resume

The Erase Suspend command allows the system to interrupt a sector erase operation and then

program or read data from a different sector within the same plane. Since this device has a mul-

tiple plane architecture, there is no need to use the erase suspend feature while erasing a sector

when you want to read data from a sector in another plane. After the Erase Suspend command

is given, the device requires a maximum time of 15 µs to suspend the erase operation. After the

erase operation has been suspended, the plane that contains the suspended sector enters the

erase-suspend-read mode. The system can then read data or program data to any other sector

within the device. An address is not required during the Erase Suspend command. During a sec-

tor erase suspend, another sector cannot be erased. To resume the sector erase operation, the

system must write the Erase Resume command. The Erase Resume command is a one-bus

cycle command, which does require the plane address. The device also supports an erase sus-

pend during a complete chip erase. While the chip erase is suspended, the user can read from

any sector within the memory that is protected. The command sequence for a chip erase sus-

pend and a sector erase suspend are the same.

3.10 Program Suspend/Program Resume

The Program Suspend command allows the system to interrupt a programming operation and

then read data from a different word within the memory. After the Program Suspend command is

given, the device requires a maximum of 10 µs to suspend the programming operation. After the

programming operation has been suspended, the system can then read from any other word

within the device. An address is not required during the program suspend operation. To resume

the programming operation, the system must write the Program Resume command. The

program suspend and resume are one-bus cycle commands. The command sequence for the

3451D–FLASH–04/06

AT49BV6416(T)

erase suspend and program suspend are the same, and the command sequence for the erase

resume and program resume are the same.

3.11 128-Bit Protection Register

The AT49BV6416(T) contains a 128-bit register that can be used for security purposes in sys-

tem design. The protection register is divided into two 64-bit blocks. The two blocks are

designated as block A and block B. The data in block A is non-changeable and is programmed

at the factory with a unique number. The data in block B is programmed by the user and can be

locked out such that data in the block cannot be reprogrammed. To program block B in the pro-

tection register, the four-bus cycle Program Protection Register command must be used as

shown in the “Command Definition Table” on page 12. To lock out block B, the four-bus cycle

lock protection register command must be used as shown in the Command Definition table. Data

bit D1 must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are

don’t cares. To determine whether block B is locked out, the status of Block B Protection com-

mand is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be

reprogrammed. Please see the “Protection Register Addressing Table” on page 13 for the

address locations in the protection register. To read the protection register, the Product ID Entry

command is given followed by a normal read operation from an address within the protection

the Product ID Exit command must be given prior to performing any other operation.

3.12 Common Flash Interface (CFI)

Common Flash Interface (CFI) is a published, standardized data structure that may be read from

a Flash device. CFI allows system software to query the installed device to determine the config-

urations, various electrical and timing parameters, and functions supported by the device. CFI is

used to allow the system to learn how to interface to the Flash device most optimally. The two

primary benefits of using CFI are ease of upgrading and second source availability. The com-

mand to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h

to address 55h. The CFI Query command can be written when the device is ready to read data

or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the

system can read CFI data at the addresses given in the “Common Flash Interface Definition

Table” on page 25. To exit the CFI Query mode, the product ID exit command must be given.

3.13 Hardware Data Protection

Hardware features protect against inadvertent programs to the AT49BV6416(T) in the following

ways: (a) V

sense: if V

is below 1.8V (typical), the program function is inhibited. (b) V

power-on delay: once V

has reached the V

sense level, the device will automatically time-

out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE

low, CE high

or WE

high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a program cycle. (e) V

is less than V

ILPP

3.14 Input Levels

While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE

and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.

The I/O lines can be driven from 0 to V

CCQ

+ 0.6V.

3.15 Output Levels

For the AT49BV6416(T), output high levels are equal to V

CCQ

- 0.1V (not V

). For 2.7V to 3.6V

output levels, V

CCQ

must be tied to V

3451D–FLASH–04/06

AT49BV6416(T)

Figure 3-2. Data Polling Algorithm

(Configuration Register = 00)

Notes: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector

address within the sector being erased. During chip

erase, a valid address is any non-protected sector

address.

2. I/O7 should be rechecked even if I/O5 = “1” because

I/O7 may change simultaneously with I/O5.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

I/O3, I/O5 = 1?

Read I/O7 - I/O0

Addr = VA

I/O7 = Data?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Device in

Read Mode

Figure 3-3. Data Polling Algorithm

(Configuration Register = 01)

Note: 1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector

address within the sector being erased. During chip

erase, a valid address is any non-protected sector

address.

START

Read I/O7 - I/O0

Addr = VA

I/O7 = 1?

I/O3, I/O5 = 1?

Program/Erase

Operation Not

Successful, Write

Product ID

Exit Command

YES

Program/Erase

Operation

Successful,

Write Product ID

Exit Command

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

AT49BV6416-70TU

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