P89C660HBA/00,512 Datasheet P89C660HBA/00,512, P89C660HFA/00,512, P89C662HBA/00,512 | P61-P63

Philips Semiconductors Product data

P89C660/P89C662/P89C664/

P89C668

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM

2002 Oct 28

Expanded Data RAM Addressing

The P89C660/662/664/668 has internal data memory that is

mapped into four separate segments: the lower 128 bytes of RAM,

upper 128 bytes of RAM, 128 bytes Special Function Register (SFR),

and 256 bytes expanded RAM (ERAM) (256 bytes for the ’660; 768

bytes for the ’662; 1792 bytes for the ’664; 7936 bytes for the ’668).

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are

directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are

indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH)

are directly addressable only.

4. The 256/768/1792/7936-bytes expanded RAM (ERAM,

00H – XFFH/2FFH/6FFH/1FFFH) are indirectly accessed by

move external instruction, MOVX, and with the EXTRAM bit

cleared, see Figure 53.

The Lower 128 bytes can be accessed by either direct or indirect

addressing. The Upper 128 bytes can be accessed by indirect

addressing only. The Upper 128 bytes occupy the same address

space as the SFR. That means they have the same address, but are

physically separate from SFR space.

When an instruction accesses an internal location above address

7FH, the CPU knows whether the access is to the upper 128 bytes

of data RAM, or to SFR space by the addressing mode used in the

instruction. Instructions that use direct addressing, access SFR

space. For example:

MOV 0A0H,A

accesses the SFR at location 0A0H (which is P2). Instructions that

use indirect addressing, access the Upper 128 bytes of data RAM.

For example:

MOV @R0,A

where R0 contains 0A0H, accesses the data byte at address 0A0H,

rather than P2 (whose address is 0A0H).

The ERAM can be accessed by indirect addressing, with EXTRAM

bit cleared and MOVX instructions. This part of memory is physically

located on-chip, logically occupies the first 256 bytes (660), 768

(662), 1792 (664), 7936 (668) of external data memory.

With EXTRAM = 0, the ERAM is indirectly addressed, using the

MOVX instruction in combination with any of the registers R0, R1 of

the selected bank or DPTR. An access to ERAM will not affect ports

P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is in output state during

external addressing. For example, with EXTRAM = 0,

MOVX @R0,A

where R0 contains 0A0H, access the ERAM at address 0A0H rather

than external memory. An access to external data memory locations

higher than the ERAM will be performed with the MOVX DPTR

instructions in the same way as in the standard 80C51 (with P0 and

P2 as data/address bus, and P3.6 and P3.7 as write and read timing

signals. Refer to Figure 54).

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar

to the standard 80C51. MOVX @ Ri will provide an 8-bit address

multiplexed with data on Port 0 and any output port pins can be

used to output higher order address bits. This is to provide the

external paging capability. MOVX @DPTR will generate a 16-bit

address. Port 2 outputs the high-order eight address bits (the

contents of DPH) while Port 0 multiplexes the low-order eight

address bits (the contents of DPL) with data. MOVX @Ri and MOVX

@DPTR will generate either read or write signals on P3.6 (WR

) and

P3.7 (RD

The stack pointer (SP) may be located anywhere in the 256 bytes

RAM (lower and upper RAM) internal data memory. The stack may

not be located in the ERAM.

AUXR

Reset Value = xxxx xx10B

— —————EXTRAM AO

Not Bit Addressable

Bit:

Symbol Function

AO Disable/Enable ALE

AO Operating Mode

0 ALE is emitted at a constant rate of

the oscillator frequency (6 clock mode;

OSC

in 12 clock mode)

1 ALE is active only during off-chip memory access.

EXTRAM Internal/External RAM access using MOVX @Ri/@DPTR

EXTRAM Operating Mode

0 Internal ERAM access using MOVX @Ri/@DPTR

1 External data memory access.

— Not implemented, reserved for future use*.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new

bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU01711

76543210

Address = 8EH

Figure 53. AUXR: Auxiliary Register

Philips Semiconductors Product data

P89C660/P89C662/P89C664/

P89C668

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM

2002 Oct 28

ERAM

256, 768,

1792 OR 7936

BYTES

UPPER

128 BYTES

INTERNAL RAM

LOWER

128 BYTES

INTERNAL RAM

SPECIAL

FUNCTION

000

80 80

EXTERNAL

DATA

MEMORY

FFFF

0000

SU01712

FF/2FF/6FF/1FFF

Figure 54. Internal and External Data Memory Address Space with EXTRAM = 0

Hardware WatchDog Timer (One-Time Enabled

with Reset-Out for P89C660/662/664/668)

The WDT is intended as a recovery method in situations where the

CPU may be subjected to software upset. The WDT consists of a

14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The

WDT is disabled at reset. To enable the WDT, user must write 01EH

and 0E1H in sequence to the WDTRST (SFR location 0A6H). When

WDT is enabled, it will increment every machine cycle while the

oscillator is running and there is no way to disable the WDT except

through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output reset HIGH pulse at the RST

pin.

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to

the WDTRST (SFR location 0A6H). When WDT is enabled, the user

needs to service it by writing 01EH and 0E1H to WDTRST to avoid

WDT overflow. The 14-bit counter overflows when it reaches 16383

(3FFFH) and this will reset the device. When WDT is enabled, it will

increment every machine cycle while the oscillator is running. This

means the user must reset the WDT at least every 16383 machine

cycles. To reset the WDT, the user must write 01EH and 0E1H to

WDTRST. WDTRST is a write only register. The WDT counter

cannot be read or written. When the WDT overflows, it will generate

an output RESET pulse at the RST pin. The RESET pulse duration

is 98 × T

OSC

(6 clock mode; 196 in 12 clock mode), where

OSC

= 1/f

OSC

. To make the best use of the WDT, it should be

serviced in those sections of code that will periodically be executed

within the time required to prevent a WDT reset.

Philips Semiconductors Product data

P89C660/P89C662/P89C664/

P89C668

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM

2002 Oct 28

FLASH EPROM MEMORY

GENERAL DESCRIPTION

The P89C660/662/664/668 Flash memory augments EPROM

functionality with in-circuit electrical erasure and programming. The

Flash can be read and written as bytes. The Chip Erase operation

will erase the entire program memory. The Block Erase function can

erase any Flash byte block. In-System Programming and standard

parallel programming are both available. On-chip erase and write

timing generation contribute to a user-friendly programming

interface.

The P89C660/662/664/668 Flash reliably stores memory contents

even after 10,000 erase and program cycles. The cell is designed to

optimize the erase and programming mechanisms. In addition, the

combination of advanced tunnel oxide processing and low internal

electric fields for erase and programming operations, produces

reliable cycling. The P89C660/662/664/668 uses a +5 V V

supply

to perform the Program/Erase algorithms.

FEATURES – IN-SYSTEM PROGRAMMING (ISP)

AND IN-APPLICATION PROGRAMMING (IAP)

• Flash EPROM internal program memory with Block Erase.

• Internal 1 kbyte fixed boot ROM, containing low-level in-system

programming routines and a default serial loader. User program

can call these routines to perform In-Application Programming

(IAP). The Boot ROM can be turned off to provide access to the

full 64 kbyte of Flash memory.

• Boot vector allows user provided Flash loader code to reside

anywhere in the Flash memory space. This configuration provides

flexibility to the user.

• Default loader in Boot ROM allows programming via the serial port

without the need for a user provided loader.

• Up to 64 kbytes of external program memory if the internal

program memory is disabled (EA

= 0).

• Programming and erase voltage +5 V (+12 V tolerant).

• Read/Programming/Erase using ISP/IAP:

– Byte Programming (20 ms).

– Typical quick erase times:

Block Erase (8 kbytes or 16 kbytes) in 10 seconds.

Full Erase (64 kbytes) in 20 seconds.

• In-System Programming.

• Programmable security for the code in the Flash.

• 10,000 minimum erase/program cycles for each byte.

• 10-year minimum data retention.

CAPABILITIES OF THE PHILIPS 89C51

FLASH-BASED MICROCONTROLLERS

Flash organization

The P89C660/662/664/668 contains 16KB/32KB/64KB of Flash

program memory. This memory is organized as 5 separate blocks.

The first two blocks are 8 kbytes in size, filling the program memory

space from address 0 through 3FFF hex. The final three blocks are

16 kbytes in size and occupy addresses from 4000 through FFFF

hex.

Figure 55 depicts the Flash memory configurations.

Flash Programming and Erasure

There are three methods of erasing or programming of the Flash

memory that may be used. First, the Flash may be programmed or

erased in the end-user application by calling low-level routines

through a common entry point in the Boot ROM. The end-user

application, though, must be executing code from a different block

than the block that is being erased or programmed. Second, the

on-chip ISP boot loader may be invoked. This ISP boot loader will, in

turn, call low-level routines through the same common entry point in

the Boot ROM that can be used by the end-user application. Third,

the Flash may be programmed or erased using the parallel method

by using a commercially available EPROM programmer. The parallel

programming method used by these devices is similar to that used

by EPROM 87C51, but it is not identical, and the commercially

available programmer will need to have support for these devices.

Boot ROM

When the microcontroller programs its own Flash memory, all of the

low level details are handled by code that is permanently contained

in a 1 kbyte “Boot ROM” that is separate from the Flash memory.

A user program simply calls the common entry point with appropriate

parameters in the Boot ROM to accomplish the desired operation.

Boot ROM operations include things like: erase block, program byte,

verify byte, program security lock bit, etc. The Boot ROM overlays

the program memory space at the top of the address space from

FC00 to FFFF hex, when it is enabled. The Boot ROM may be

turned off so that the upper 1 kbytes of Flash program memory are

accessible for execution.

P89C660HBA/00,512

Mfr. #:

Buy P89C660HBA/00,512

Manufacturer:

NXP Semiconductors

Description:

IC MCU 8BIT 16KB FLASH 44PLCC

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P89C660HBA/00,512

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