Philips Semiconductors Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
79
AC ELECTRICAL CHARACTERISTICS (12 CLOCK MODE)
T
amb
= 0 °C to +70 °C, V
CC
= 5 V ± 10%, or –40 °C to +85 °C, V
CC
= 5 V ±5%, V
SS
= 0V
1,
2,
3
VARIABLE CLOCK
4
33 MHz CLOCK
4
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT
1/t
CLCL
57 Oscillator frequency 0 33 – – MHz
t
LHLL
57 ALE pulse width 2t
CLCL
–40 – 21 – ns
t
AVLL
57 Address valid to ALE low t
CLCL
–25 – 5 – ns
t
LLAX
57 Address hold after ALE low t
CLCL
–25 – 5 – ns
t
LLIV
57 ALE low to valid instruction in – 4t
CLCL
–65 – 55 ns
t
LLPL
57 ALE low to PSEN low t
CLCL
–25 – 5 – ns
t
PLPH
57 PSEN pulse width 3t
CLCL
–45 – 45 – ns
t
PLIV
57 PSEN low to valid instruction in – 3t
CLCL
–60 – 30 ns
t
PXIX
57 Input instruction hold after PSEN 0 – 0 – ns
t
PXIZ
57 Input instruction float after PSEN – t
CLCL
–25 – 5 ns
t
AVIV
57 Address to valid instruction in – 5t
CLCL
–80 – 70 ns
t
PLAZ
57 PSEN low to address float – 10 – 10 ns
Data Memory
t
RLRH
58, 59 RD pulse width 6t
CLCL
–100 – 82 – ns
t
WLWH
58, 59 WR pulse width 6t
CLCL
–100 – 82 – ns
t
RLDV
58, 59 RD low to valid data in – 5t
CLCL
–90 – 60 ns
t
RHDX
58, 59 Data hold after RD 0 – 0 – ns
t
RHDZ
58, 59 Data float after RD – 2t
CLCL
–28 – 32 ns
t
LLDV
58, 59 ALE low to valid data in – 8t
CLCL
–150 – 90 ns
t
AVDV
58, 59 Address to valid data in – 9t
CLCL
–165 – 105 ns
t
LLWL
58, 59 ALE low to RD or WR low 3t
CLCL
–50 3t
CLCL
+50 40 140 ns
t
AVWL
58, 59 Address valid to WR low or RD low 4t
CLCL
–75 – 45 – ns
t
QVWX
58, 59 Data valid to WR transition t
CLCL
–30 – 0 – ns
t
WHQX
58, 59 Data hold after WR t
CLCL
–25 – 5 – ns
t
QVWH
59 Data valid to WR high 7t
CLCL
–130 – 80 – ns
t
RLAZ
58, 59 RD low to address float – 0 – 0 ns
t
WHLH
58, 59 RD or WR high to ALE high t
CLCL
–25 t
CLCL
+25 5 55 ns
External Clock
t
CHCX
61 High time 17 t
CLCL
–t
CLCX
– – ns
t
CLCX
61 Low time 17 t
CLCL
–t
CHCX
– – ns
t
CLCH
61 Rise time – 5 – – ns
t
CHCL
61 Fall time – 5 – – ns
Shift Register
t
XLXL
60 Serial port clock cycle time 12t
CLCL
– 360 – ns
t
QVXH
60 Output data setup to clock rising edge 10t
CLCL
–133 – 167 – ns
t
XHQX
60 Output data hold after clock rising edge 2t
CLCL
–80 – 50 – ns
t
XHDX
60 Input data hold after clock rising edge 0 – 0 – ns
t
XHDV
60 Clock rising edge to input data valid – 10t
CLCL
–133 – 167 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
= 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.
