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series with the compensation capacitor. The resistor in
series with the capacitor creates a zero in the current limit
loop transfer function given by:
f
Z
=
1
2 π R
Z
C
while minimally impacting the frequency of the compensa-
tion pole. Given the current limit loop frequency response
contains several moderate frequency poles: one at approxi-
mately
10
kHz (typical) and two at approximately 100kHz
(typical),
the placement of the zero in frequency can be
used to provide additional phase margin, which in turn,
may allow a higher loop bandwidth without sacrificing
loop stability. For example, choosing C = 0.33µF and R
Z
=
50 creates a zero at approximately 10kHz thereby reduc-
ing the impact of the internal pole located at that same
frequency
.
With this compensation scheme, the LTC3626
current limit loop will have a dominant pole frequency, and
overall loop bandwidth, roughly three times higher than
that provided with a F capacitor, while likely providing
adequate loop stability.
As previously described, the LTC3626 senses the average
output current through the synchronous FET during the
off time. As a result, it is recommended the LTC3626 be
operated with an off time of greater than 150ns for best
current monitor accuracy. For many applications, this
is of little concern unless operating at or near regulator
dropout conditions (extremely high duty-cycle operation)
and high switching frequencies. Overall, best current
monitor accuracy is achieved with output currents above
approximately 200mA in forced continuous mode with
switching frequencies of 1MHz or lower.
On-Die Temperature Monitor and Limit
The LTC3626 produces a voltage at the TMON pin propor
-
tional to the measured junction temperature. The junction
temperature-to-voltage scaling factor is 200°K/V.
Thus,
to obtain the junction temperature in degrees Kelvin,
simply multiply the voltage provided at the TMON pin by
the scaling factor. To obtain the junction temperature in
degrees Celsius, subtract 273 from the value obtained in
degrees Kelvin.
The temperature monitor function uses a chopping tech
-
nique to achieve high precision. As a result
, a small periodic
ripple may be seen at the TMON pin, the average of which
is the measured value of interest. The ripple frequency will
be the operating frequency divided by 32. If required, a
F or greater capacitor to SGND may be placed on the
output to reduce the magnitude of the ripple.
The temperature monitor output is driven from a flexible,
internally compensated on-chip buffer capable of sourcing
or sinking small amounts of continuous currents (<20µA
typical). The buffer internal compensation is intended
for capacitive loads up to approximately 150pF (typical).
This configuration allows direct connection of TMON to
convenient test equipment, such as a multimeter, for
temperature measurement. The internal compensation
may be overridden by connecting a capacitor of value 1µF
or greater between TMON and SGND. This configuration
allows for a wide range of applications requiring stability
with higher load capacitance, such as some ADC inputs.
The voltage produced at TMON is continuously fed to
a limit comparator that has the voltage at the TSET pin
as its reference input. When triggered, this comparator
generates an overtemperature fault that will initiate part
shutdown and reset of soft-start. Thus, a programmable
temperature limit may be obtained by providing a voltage
at the TSET pin that corresponds to the temperature limit
of interest. The voltage at the TSET pin may be derived
from a resistor divider from INTV
CC
, subject to the current
constraints listed in the Electrical Characteristics section,
or may be driven externally. The LTC3626 will clear the
overtemperature fault and attempt to restart once the in
-
ternal temperature falls 10°C (typical)
from the threshold
given at TSET. As an example, to set a temperature limit
at approximately 125°C, the voltage at TSET should be:
V
TSET
=
125
°
C
+
273
200
°
K/V
2V
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above. During normal operation, if the output drops below
10% of its final value, as it may when tracking down for
instance, the regulator will automatically switch to Burst
Mode operation to prevent inductor saturation and improve
TRACK/SS pin accuracy.
Output Power Good
The PGOOD output of the LTC3626 is driven by a 20Ω
(typical) open-drain pull-down device. This pin will become
high impedance once the output voltage is within 5%
(typical) of the target regulation point allowing the volt
-
age at PGOOD to rise via an external pull-up resistor. If
the output
voltage exits a 8% (typical) regulation window
around the target regulation point, the open-drain output
will pull down to ground, thereby dropping the PGOOD
pin voltage. A filter time of 40μs (typical) acts to prevent
unwanted PGOOD output changes during V
OUT
transient
events. As a result, the output voltage must be within
the target regulation window of 5% for 40μs before the
PGOOD pin is pulled high. Conversely, the output voltage
must exit the 8% regulation window for 40μs before the
PGOOD pin pulls to ground (see Figure 4).
PGOOD
VOLTAGE
V
OUT
–8% –5% 5% 8%
3626 F04
0%
NOMINAL OUTPUT
Figure 4. PGOOD Pin Behavior
MODE/SYNC Operation
The MODE/SYNC pin is a multipurpose pin allowing both
mode selection and operating frequency synchronization.
Connecting this pin to INTV
CC
enables Burst Mode operation
for superior efficiency at low load currents at the expense
of slightly higher output voltage ripple. When the MODE/
SYNC pin is pulled to ground, forced continuous mode
operation is selected creating the lowest output voltage
ripple at the expense of light load efficiency.
The LTC3626 will detect the presence of an external clock
signal on the MODE/SYNC pin and synchronize the internal
oscillator to the phase and frequency of the incoming clock.
The presence of an external clock will place the LTC3626
into forced continuous mode operation.
Output Voltage Tracking and Soft-Start
The LTC3626 allows the user to control the output volt
-
age ramp rate by means of the TRACK/SS pin. From 0V
to 0.6V the TRACK
/SS pin will override the internal refer-
ence input to the error amplifier forcing regulation of the
feedback voltage to that seen at the TRACK
/
SS pin. When
the voltage at the TRACK/SS pin rises above 0.6V, tracking
is disabled and the feedback voltage will be regulated to
the internal reference voltage.
The voltage at the TRACK/SS pin may be driven from an
external source, or alternatively, the user may leverage the
internal 1.4µA (typical) pull-up current on TRACK/SS to
implement a soft-start function by connecting a capacitor
from the TRACK/SS pin to ground. The relationship between
output rise time and TRACK/SS capacitance is given by:
t
SS
= 430,000 C
TRACK/SS
A default internal soft-start timer forces a minimum soft-
start time of 400µs (typical) by overriding the TRACK/
SS pin input during this time period. Hence, capacitance
values less than approximately 1000pF will not significantly
affect soft-start behavior.
When using the TRACK/SS pin, the regulator defaults to
Burst Mode operation until the output exceeds 80% of
its final value (V
FB
> 0.48V). Once the output reaches this
voltage, the operating mode of the regulator switches to
the mode selected by the MODE/SYNC pin as described
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual loss terms as a per
-
centage of input power.
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Although all dissipative elements in the circuit produce
losses, three main sources account for the majority of the
losses in the LTC3626: 1) I
2
R loss, 2) switching losses
and quiescent current loss, 3) transition losses and other
system losses.
1. I
2
R loss is calculated from the DC resistance of the
internal switches, R
SW
, and external inductor, R
L
.
In continuous mode, the average output current will
flow through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both the top and bottom MOSFETs R
DS(ON)
and the
duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) +(R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I
2
R loss:
I
2
R Loss” = I
OUT
2
(R
SW
+ R
L
)
2. The internal LDO supplies the power to the INTV
CC
rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge, dQ, moves
from SV
IN
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the DC
control bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the
internal top and bottom power MOSFETs and f is the
switching frequency. For estimation purposes, (Q
T
+
Q
B
) on the LTC3626 is approximately 2.5nC. To calculate
the total power loss from the LDO load, simply add the
gate charge current and quiescent current and multiply
by SV
IN
:
P
LDO
= (I
GATECHG
+ I
Q
) V
IN
3. Other “hidden” losses such as transition loss, cop-
per trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system
.
Transition loss arises from the
brief amount of time the top power MOSFET spends in
the saturated region during switch node transitions.
Other losses, including diode conduction losses during
dead time and inductor core losses, generally account for
less than 2% total additional loss.
Thermal Considerations
The LTC3626 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to provide
good thermal contact. This gives the QFN package excep
-
tional thermal properties, compared to other packages
of similar size,
making it difficult in normal operation to
exceed the maximum junction temperature of the part. In
many applications, the LTC3626 does not generate much
heat due to its high efficiency and low thermal resistance
package backplane. However, in applications in which
the LTC3626 is running at a high ambient temperature,
high input voltage, high switching frequency, and maxi
-
mum output current, the generated heat may exceed the
maximum junction temperature of the part
.
If the junction
temperature reaches approximately 175°C, both power
switches will be turned off until temperature decreases
approximately 10°C.
Thermal analysis should always be performed by the user
to ensure the LTC3626 does not exceed the maximum
junction temperature.
The temperature rise is given by:
T
RISE
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
Consider the example in which an LTC3626EUDC is operat
-
ing with I
OUT
= 2.5A, PV
IN
= SV
IN
= 12V, f = 2MHz, V
OUT
= 1.8V, and an ambient temperature of 70°C. From the
Typical Per
formance Characteristics section the R
DS(ON)
of the top switch is found to be nominally 130mΩ while
that of the bottom switch is nominally 85mΩ yielding an
equivalent power MOSFET resistance R
SW
of:
R
DS(ON)TOP
1.8
12
+R
DS(ON)BOT
10.2
12
=92m
W

LTC3626IUDC#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3A, 20V Monolithic Step-Down Regulator with Current and Temperature Monitoring
Lifecycle:
New from this manufacturer.
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