Pin# Pin Name Type Description
1 FB_DNC# DNC
Complement clock of differential feedback. The feedback output
and feedback input are connected internally on this pin. Do not
connect anything to this pin.
2 VDDR1.8 PWR
1.8V power for differential input clock (receiver). This VDD should
be treated as an Analog power rail and filtered appropriately.
3 CLK_IN IN True Input for differential reference clock.
4 CLK_IN# IN Complementary Input for differential reference clock.
5 GNDR GND Analog Ground pin for the differential input (receiver)
6 GNDDIG GND Ground pin for digital circuitry
7 VDDDIG1.8 PWR 1.8V digital power (dirty power)
8 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
9 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
10 GND GND Ground pin.
11 VDDO1.8 PWR Power supply for outputs, nominally 1.8V.
12 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-
down.
1 =disable outputs, 0 = enable outputs
13 DIF0 OUT Differential true clock output
14 DIF0# OUT Differential Complementary clock output
15 GNDA GND Ground pin for the PLL core.
16 VDDA1.8 PWR 1.8V power for the PLL core.
17 DIF1 OUT Differential true clock output
18 DIF1# OUT Differential Complementary clock output
19 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-
down.
1 =disable outputs, 0 = enable outputs
20 VDDO1.8 PWR Power supply for outputs, nominally 1.8V.
21 GND GND Ground pin.
22 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first
high assertion. Low enters Power Down Mode, subsequent high
assertions exit Power Down Mode. This pin has internal pull-up
resistor.
23 ^vHIBW_BYPM_LOBW#
LATCHED
IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
24 FB_DNC DNC
True clock of differential feedback. The feedback output and
feedback input are connected internally on this pin. Do not connect
anything to this pin.
25 ePad GND Connect epad to ground.
