1. General description
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a
clock input (CP), an up/down count control input (UP/DN
), an active LOW count enable
input (CE
), an asynchronous active HIGH parallel load input (PL), four parallel inputs
(D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC
),
and an overriding asynchronous master reset input (MR).
Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all
other input conditions except for MR which must be LOW. When PL and CE
are LOW, the
counter changes on the LOW-to-HIGH transition of CP. Input UP/DN
determines the
direction of the count, counting up when HIGH and counting down when LOW. When
counting up, TC
is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting
down, TC
is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter
(Q0 to Q3 = LOW) independent of all other input conditions.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
HEF4516B
Binary up/down counter
Rev. 7 — 11 November 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C.
Type number Package
Name Description Version
HEF4516BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4
HEF4516BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
