HEF4516B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 10 of 17
NXP Semiconductors
HEF4516B
Binary up/down counter
11. Waveforms
Table 8. Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; C
L
= 50 pF; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) Where:
P
D
dynamic power
dissipation
5 V P
D
= 1000 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 4500 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 11200 f
i
+ (f
o
C
L
) V
DD
2
Measurement points are given in Table 9.
Fig 6. Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP
Measurement points are given in Table 9.
Fig 7. Waveforms showing PL and MR minimum pulse widths and recovery times, and Dn to PL set-up and hold
times
001aae673
CP input
V
I
V
SS
V
SS
V
SS
V
SS
V
I
V
I
V
I
PL input
Dn input
V
M
t
W
t
rec
V
M
MR input
t
rec
V
M
t
W
V
M
t
h
t
su
HEF4516B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 11 of 17
NXP Semiconductors
HEF4516B
Binary up/down counter
a. Input waveforms
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test
C
L
= Load capacitance including jig and probe capacitance;
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
V
DD
V
I
V
O
001aag182
DUT
C
L
R
T
G
Table 9. Measurement points and test data
Supply voltage Input Load
V
I
V
M
t
r
, t
f
C
L
5Vto15V V
DD
0.5V
I
20 ns 50 pF
HEF4516B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 11 November 2011 12 of 17
NXP Semiconductors
HEF4516B
Binary up/down counter
12. Package outline
Fig 9. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT38-4
95-01-14
03-02-13
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
b
2
e
D
A
2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT
A
max.
12
b
1
(1) (1)
(1)
b
2
cD E e M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
0.764.2 0.51 3.2
inches
0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12
0.010.1 0.3
0.32
0.31
0.39
0.33
0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4

HEF4516BT,653

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers BINARY U/D COUNTER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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