MAX1068CCEG+ Datasheet MAX1068AEEG+, MAX1068CCEG+, MAX1067BEEE+ | P10-P12

MAX1067/MAX1068

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

10 ______________________________________________________________________________________

Pin Description

MAX1067

MAX1068

NAME

FUNCTION

DOUT

Serial Data Output. Data changes state on SCLK’s falling edge in SPI/QSPI/MICROWIRE

mode and on SCLK’s rising edge in DSP mode (MAX1068 only). DOUT is high impedance

when CS is high.

SCLK

Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks

data out.

3 5 DIN

Serial Data Input. Use DIN to communicate with the command/configuration/control register.

In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In DSP

mode, the falling edge of SCLK clocks in data at DIN.

46EOC

End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a

conversion with the result available at DOUT. In external clock mode, EOC remains high.

5 7 AIN0 Analog Input 0

6 8 AIN1 Analog Input 1

7 9 AIN2 Analog Input 2

8 10 AIN3 Analog Input 3

9 15 REF

Reference Voltage Input/Output. V

REF

sets the analog voltage range. Bypass to AGND with

a 10µF capacitor. Bypass with a 1µF (min) capacitor when using the internal reference.

10 16

REFCAP

Refer ence Byp ass C ap aci tor C onnecti on. Byp ass to AG N D w i th a 0.1µF cap aci tor w hen usi ng

i nter nal r efer ence. Inter nal r efer ence and b uffer shut d ow n i n exter nal r efer ence m od e.

11 17

AGND

Analog Ground. Connect to pin 18 (MAX1068) or pin 12 (MAX1067).

12 18

AGND

Primary Analog Ground (Star Ground). Power return for AV

13 19

Analog Supply Voltage. Bypass to AGND with a 0.1µF capacitor.

14 20 CS

Active-Low Chip-Select Input. Forcing CS high places the MAX1067/MAX1068 in shutdown

with a typical supply current of 0.6µA. In SPI/QSPI/MICROWIRE mode, a high-to-low

transition on CS activates normal operating mode. In DSP mode, after the initial CS transition

from high to low, CS can remain low for the entire conversion process (see the Operating

Modes section).

15 21

DGND

Digital Ground

16 22

Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.

—1

DSPR

DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a

conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode.

—2

DSEL

Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide data-

transfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not leave

DSEL unconnected.

— 11 AIN4 Analog Input 4

— 12 AIN5 Analog Input 5

Detailed Description

The MAX1067/MAX1068 low-power, multichannel, 14-

bit ADCs feature a successive-approximation ADC,

automatic power-down, integrated +4.096V reference,

and a high-speed SPI/QSPI/MICROWIRE-compatible

interface. A DSPR input and DSPX output allow the

MAX1068 to communicate with DSPs with no external

glue logic. The MAX1067/MAX1068 operate with a sin-

gle +5V analog supply and feature a separate digital

supply allowing direct interfacing with +2.7V to +5.5V

digital logic.

Figures 3 and 4 show the functional diagrams of the

MAX1067/MAX1068, and Figures 5 and 6 show the

MAX1067/MAX1068 in a typical operating circuit. The

serial interface simplifies communication with micro-

processors (µPs).

In external reference mode, the MAX1067/MAX1068

have two power modes: normal mode and shutdown

mode. Driving CS high places the MAX1067/MAX1068

in shutdown mode, reducing the supply current to

0.6µA (typ). Pull CS low to place the MAX1067/

MAX1068 in normal operating mode. The internal refer-

ence mode offers software-programmable, power-down

options as shown in Table 5.

In SPI/QSPI/MICROWIRE mode, a falling edge on CS

wakes the analog circuitry and allows SCLK to clock in

data. Acquisition and conversion are initiated by SCLK.

The conversion result is available at DOUT in unipolar

serial format. DOUT is held low until data becomes

available (MSB first) on the 8th falling edge of SCLK

when in 8-bit transfer mode, and on the 16th falling

edge when in 16-bit transfer mode. See the Operating

Modes section. Figure 8 shows the detailed SPI/QSPI/

MICROWIRE serial-interface timing diagram.

In external clock mode, the MAX1068 also interfaces

with DSPs. In DSP mode, a frame-sync pulse from the

DSP initiates a conversion that is driven by SCLK. The

MAX1068 formats a frame-sync pulse to notify the DSP

that the conversion results are available at DOUT in

MSB-first, unipolar, serial-data format. Figure 16 shows

the detailed DSP serial-interface timing diagram (see the

Operating Modes section).

Analog Input

Figure 7 illustrates the input-sampling architecture of

the ADC. The voltage applied at REF or the internal

+4.096V reference sets the full-scale input voltage.

Track/Hold (T/H)

In track mode, the analog signal is acquired on the

internal hold capacitor. In hold mode, the T/H switches

open and the capacitive digital-to-analog converter

(DAC) samples the analog input.

MAX1067/MAX1068

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

______________________________________________________________________________________ 11

Pin Description (continued)

MAX1067

MAX1068

NAME

FUNCTION

— 13 AIN6 Analog Input 6

— 14 AIN7 Analog Input 7

—23

DSPX

DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the

MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode.

— 24 N.C. No Connection. Not internally connected.

DGND

1mA

LOAD

= 30pF

DOUT

LOAD

= 30pF

1mA

DGND

a) V

TO V

b) HIGH-Z TO V

AND V

TO V

Figure 1. Load Circuits for DOUT Enable Time and SCLK-to-

DOUT Delay Time

DGND

1mA

LOAD

= 30pF

DOUT

LOAD

= 30pF

1mA

DGND

a) V

TO HIGH-Z

b) V

TO HIGH-Z

Figure 2. Load Circuits for DOUT Disable Time

MAX1067/MAX1068

During the acquisition, the analog input (AIN_) charges

capacitor C

DAC

. At the end of the acquisition interval

the T/H switches open. The retained charge on C

DAC

represents a sample of the input.

In hold mode, the capacitive DAC adjusts during the

remainder of the conversion cycle to restore node

ZERO to zero within the limits of 14-bit resolution. At the

end of the conversion, force CS high and then low to

reset the T/H switches back to track mode (AIN_),

where C

DAC

charges to the input signal again.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens and more time must be

allowed between conversions. The acquisition time

ACQ

) is the maximum time the device takes to acquire

the signal. Use the following formula to calculate acqui-

sition time:

ACQ

= 11(R

+ R

DS(ON)

) ✕ 45pF + 0.3µs

where R

= 340Ω, R

= the input signal’s source

impedance, R

DS(ON)

= 60Ω, and t

ACQ

is never less

than 729ns. A source impedance less than 200Ω does

not significantly affect the ADC’s performance. The

MAX1068 features a 16-bit-wide data-transfer mode

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

12 ______________________________________________________________________________________

REFERENCE

REF

REFCAP

AGND

AGND DGND

AIN0

AIN1

AIN2

AIN3

SCLK

DIN

ANALOG-INPUT

MULTIPLEXER

CONTROL

ACCUMULATOR

MEMORY

INPUT REGISTER

BIAS

OSCILLATOR

OUTPUT DOUT

EOC

ANALOG-SWITCH FINE TIMING

SUCCESSIVE-APPROXIMATION

MAX1067

DAC

BUFFER

RAIL

COMPARATOR

Figure 3. MAX1067 Functional Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

MAX1068CCEG+

Mfr. #:

Buy MAX1068CCEG+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps

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MAX1068CCEG+

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