MAX1068CCEG+ Datasheet MAX1068AEEG+, MAX1068CCEG+, MAX1067BEEE+ | P16-P18

MAX1067/MAX1068

Power-Down Modes

Table 5 shows the MAX1067/MAX1068 power-down

modes. Three internal reference modes and one exter-

nal reference mode are available. Select power-down

modes by writing to bits 2 and 1 in the command/con-

figuration/control register. The MAX1067/MAX1068

enter the selected power-down mode on the rising

edge of CS.

The internal reference stays on when CS is pulled high,

if bits 2 and 1 are set to zero. This mode allows for the

fastest turn-on time.

Setting bit 2 = 0 and bit 1 = 1 turns both the reference

and reference buffer off when CS is brought high. This

mode achieves the lowest supply current. The refer-

ence and buffer wake up on the falling edge of CS

when in SPI/QSPI/MICROWIRE mode and on the falling

edge of DSPR when in DSP mode. Allow 5ms for the

internal reference to rise and settle when powering up

from a complete shutdown (V

REF

= 0, C

REF

= 1µF).

The internal reference stays on and the buffer is shut off

on the rising edge of CS when bit 2 = 1 and bit 1 = 0.

The MAX1067/MAX1068 enter this mode on the rising

edge of CS. The buffer wakes up on the falling edge of

CS when in SPI/QSPI/MICROWIRE mode and on the

falling edge of DSPR when in DSP mode. Allow 5ms for

REF

to settle when powering up from a complete shut-

down (V

REF

= 0, C

REF

= 1µF). V

REFCAP

is always equal

to +4.096V in this mode.

Set both bit 2 and bit 1 to 1 to turn off the reference and

reference buffer to allow connection of an external ref-

erence. Using an external reference requires no extra

wake-up time.

Operating Modes

External Clock 8-Bit-Wide Data-Transfer Mode

(MAX1067 and MAX1068)

Force DSPR high and DSEL low (MAX1068) for SPI/

QSPI/MICROWIRE-interface mode. The falling edge of CS

wakes the analog circuitry and allows SCLK to clock in

data. Ensure the duty cycle on SCLK is between 45% and

55% when operating at 4.8MHz (the maximum clock fre-

quency). For lower clock frequencies, ensure the

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

16 ______________________________________________________________________________________

SCLK

DIN

DOUT

CSW

CSS

CSH

• • •

Figure 8. Detailed SPI Interface Timing

COMPLETE CONVERSION SEQUENCE

CONVERSION 0

CONVERSION 1

POWERED UP

POWERED DOWN

DOUT

Figure 9. Shutdown Sequence

minimum high and low times are at least 93ns. External

clock-mode conversions with SCLK rates less than

125kHz can reduce accuracy due to leakage of the sam-

pling capacitor. DOUT changes from high-Z to logic low

after CS is brought low. Input data latches on the rising

edge of SCLK. The first SCLK rising edge begins loading

data into the command/configuration/control register from

DIN. The devices select the proper channel for conver-

sion on the rising edge of the 3rd SCLK cycle. Acquisition

begins immediately thereafter and ends on the falling

edge of the 6th clock cycle. The MAX1067/MAX1068

sample the input and begin conversion on the falling

edge of the 6th clock cycle. Setup and configuration of

the MAX1067/MAX1068 complete on the rising edge of

the 8th clock cycle. The conversion result is available

(MSB first) at DOUT on the falling edge of the 8th SCLK

cycle. To read the entire conversion result, 16 SCLK

cycles are needed. Extra clock pulses, occurring after the

conversion result has been clocked out and prior to the

rising edge of CS, cause zeros to be clocked out of

DOUT. The MAX1067/MAX1068 external clock 8-bit-wide

data-transfer mode requires 24 SCLK cycles for comple-

tion (Figure 10).

Force CS high after the conversion result is read. For

maximum throughput, force CS low again to initiate the

next conversion immediately after the specified mini-

mum time (t

CSW

). Forcing CS high in the middle of a

conversion immediately aborts the conversion and

places the MAX1067/MAX1068 in shutdown.

External Clock 16-Bit-Wide Data-Transfer Mode

(MAX1068 Only)

Force DSPR high and DSEL high for SPI/QSPI/

MICROWIRE-interface mode. Logic high at DSEL allows

the MAX1068 to transfer data in 16-bit-wide words. The

acquisition time is extended an extra eight SCLK cycles

in the 16-bit-wide data-transfer mode. The falling edge

of CS wakes the analog circuitry and allows SCLK to

clock in data. Ensure the duty cycle on SCLK is

between 45% and 55% when operating at 4.8MHz (the

maximum clock frequency). For lower clock frequen-

cies, ensure that the minimum high and low times are at

least 93ns. External-clock-mode conversions with SCLK

rates less than 125kHz can reduce accuracy due to

leakage of the sampling capacitor. DOUT changes from

high-Z to logic low after CS is brought low. Input data

latches on the rising edge of SCLK. The first SCLK rising

edge begins loading data into the command/configura-

tion/control register from DIN. The devices select the

proper channel for conversion and begin acquisition on

the rising edge of the 3rd SCLK cycle. Setup and con-

figuration of the MAX1068 completes on the rising edge

of the 8th clock cycle. Acquisition ends on the falling

edge of the 14th SCLK cycle. The MAX1068 samples

the input and begins conversion on the falling edge of

the 14th clock cycle. The conversion result is available

(MSB first) at DOUT on the falling edge of the 16th

SCLK cycle. To read the entire conversion result, 16

SCLK cycles are needed. Extra clock pulses, occurring

after the conversion result has been clocked out and

MAX1067/MAX1068

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

______________________________________________________________________________________ 17

DOUT

SCLK

DIN

DSPR*

*MAX1068 ONLY

MSB LSB

S1 S0

ACQ

IDLE

CONV

ADC

STATE

DSEL*

Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing

MAX1067/MAX1068

prior to the rising edge of CS, cause zeros to be

clocked out of DOUT. The MAX1068 external clock 16-

bit-wide data-transfer mode requires 32 SCLK cycles for

completion (Figure 11).

Force CS high after the conversion result is read. For

maximum throughput, force CS low again to initiate the

next conversion immediately after the specified mini-

mum time (t

CSW

). Forcing CS high in the middle of a

conversion immediately aborts the conversion and

places the MAX1068 in shutdown.

Internal Clock 8-Bit-Wide Data-Transfer and

Scan Mode (MAX1067 and MAX1068)

Force DSPR high and DSEL low (MAX1068) for the SPI/

QSPI/MICROWIRE-interface mode. The falling edge of

CS wakes the analog circuitry and allows SCLK to

clock in data (Figure 12). DOUT changes from high-Z

to logic low after CS is brought low. Input data latches

on the rising edge of SCLK. The command/configura-

tion/control register begins reading DIN on the first

SCLK rising edge and ends on the rising edge of the

8th SCLK cycle. The MAX1067/MAX1068 select the

proper channel for conversion on the rising edge of the

3rd SCLK cycle. The internal oscillator activates 125ns

after the rising edge of the 8th SCLK cycle. Turn off the

external clock while the internal clock is on. Turning off

SCLK ensures the lowest noise performance during

acquisition. Acquisition begins on the 2nd rising edge

of the internal clock and ends on the falling edge of the

6th internal clock cycle. Each bit of the conversion

result shifts into memory as it becomes available. The

conversion result is available (MSB first) at DOUT on

the falling edge of EOC. The internal oscillator and ana-

log circuitry are shut down on the high-to-low EOC tran-

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

18 ______________________________________________________________________________________

DOUT

SCLK

DIN

DSPR

DSEL

MSB

LSB

MSB

LSB

S1 S0

ADC

STATE

16 24 32

XXXXX

X = DON

T CARE

ACQ

IDLE

CONV

Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)

DOUT

SCLK

DIN

EOC

MSB

LSB

S1 S0 X

ACQ

IDLE

CONV

POWER-DOWN

ADC

STATE

X = DON

T CARE

DSPR = DV

, DSEL = GND (MAX1068 ONLY)

INTERNAL

CLK

26 25

16924

• • •

MSB

Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

MAX1068CCEG+

Mfr. #:

Buy MAX1068CCEG+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MAX1068CCEG+

MAX1068CCEG+

Products related to this Datasheet