MAX1068CCEG+ Datasheet MAX1068AEEG+, MAX1068CCEG+, MAX1067BEEE+ | P19-P21

sition. Use the EOC high-to-low transition as the signal

to restart the external clock (SCLK). To read the entire

conversion result, 16 SCLK cycles are needed. Extra

clock pulses, occurring after the conversion result has

been clocked out and prior to the rising edge of CS,

cause the conversion result to be shifted out again. The

MAX1067/MAX1068 internal clock 8-bit-wide data-

transfer mode requires 24 external clock cycles and 25

internal clock cycles for completion.

Force CS high after the conversion result is read. For

maximum throughput, force CS low again to initiate the

next conversion immediately after the specified mini-

mum time (t

CSW

). Forcing CS high in the middle of a

conversion immediately aborts the conversion and

places the MAX1067/MAX1068 in shutdown.

Scan mode allows multiple channels to be scanned

consecutively or one channel to be scanned eight

times. Scan mode can only be enabled when using the

MAX1067/MAX1068 in the internal clock mode. Enable

scanning by setting bits 4 and 3 in the command/con-

figuration/control register (see Tables 3 and 4). In scan

mode, conversion results are stored in memory until the

completion of the last conversion in the sequence.

Upon completion of the last conversion in the

sequence, EOC transitions from high to low to indicate

the end of the conversion and shuts down the internal

oscillator. Use the EOC high-to-low transition as the sig-

nal to restart the external clock (SCLK). DOUT provides

the conversion results in the same order as the channel

conversion process. The MSB of the first conversion is

available at DOUT on the falling edge of EOC (Figure 14).

MAX1067/MAX1068

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

______________________________________________________________________________________ 19

DOUT

SCLK

DIN

EOC

X X X X X X X X

DATA

LSB

S1 S0 X

ACQ

CONFIGURATION

X = DON

T CARE

DSPR = DSEL = DV

CONV

POWER-DOWN

ADC

STATE

INTERNAL

CLK

89 16

21332

2417 32

• • •• • •

• • • • • •

MSB

Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)

DOUT

SCLK

DIN

EOC

ADC

STATE

INTERNAL

CLK

940

• • •

3026

• • • • • •

MSB

LSB

S1 S0 X

MSB

ACQ

CONFIGURATION

POWER-DOWN

CONV

ACQ

CONV

X = DON

T CARE

DSPR = DV

, DSEL = GND (MAX1068 ONLY)

Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing

MAX1067/MAX1068

Internal Clock 16-Bit-Wide Data-Transfer and

Scan Mode (MAX1068 Only)

Force DSPR high and DSEL low for the SPI/QSPI/

MICROWIRE-interface mode. The falling edge of CS

wakes the analog circuitry and allows SCLK to clock in

data (see Figure 13). DOUT changes from high-Z to logic

low after CS is brought low. Input data latches on the ris-

ing edge of SCLK. The command/configuration/control

edge and ends on the rising edge of the 8th SCLK

cycle. The MAX1068 selects the proper channel for

conversion on the rising edge of the 3rd SCLK cycle.

The internal oscillator activates 125ns after the rising

edge of the 16th SCLK cycle. Turn off the external

clock while the internal clock is on. Turning off SCLK

ensures lowest noise performance during acquisition.

Acquisition begins on the 2nd rising edge of the inter-

nal clock and ends on the falling edge of the 18th inter-

nal clock cycle. Each bit of the conversion result shifts

into memory as it becomes available. The conversion

result is available (MSB first) at DOUT on the falling

edge of EOC. The internal oscillator and analog circuit-

ry are shut down on the EOC high-to-low transition. Use

the EOC high-to-low transition as the signal to restart

the external clock (SCLK). To read the entire conver-

sion result, 16 SCLK cycles are needed. Extra clock

pulses, occurring after the conversion result has been

clocked out and prior to the rising edge of CS, cause

the conversion result to be shifted out again. The

MAX1068 internal-clock 16-bit-wide data-transfer mode

requires 32 external clock cycles and 32 internal clock

cycles for completion.

Force CS high after the conversion result is read. For

maximum throughput, force CS low again to initiate the

next conversion immediately after the specified mini-

mum time (t

CSW

). Forcing CS high in the middle of a

conversion immediately aborts the conversion and

places the MAX1068 in shutdown.

Scan mode allows multiple channels to be scanned

consecutively or one channel to be scanned eight

times. Scan mode can only be enabled when using the

MAX1068 in internal clock mode. Enable scanning by

setting bits 4 and 3 in the command/configuration/con-

trol register (see Tables 3 and 4). In scan mode, conver-

sion results are stored in memory until the completion of

the last conversion in the sequence. Upon completion of

the last conversion in the sequence, EOC transitions

from high to low to indicate the end of the conversion

and shuts down the internal oscillator. Use the EOC

high-to-low transition as the signal to restart the external

clock (SCLK). DOUT provides the conversion results in

the same order as the channel conversion process. The

MSB of the first conversion is available at DOUT on the

falling edge of EOC. Figure 15 shows the timing dia-

gram for 16-bit-wide data transfer in scan mode.

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

20 ______________________________________________________________________________________

DOUT

SCLK

DIN

EOC

ADC

STATE

INTERNAL

CLK

89 16

• • • • • •• • • • • •

X = DON

T CARE

32 34

• • • • • •

X X X X X X X X

DATA

LSB

S1 S0 X

• • •

ACQ

POWER-DOWNt

CONV

ACQ

CONV

MSB

Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1068 Only)

DSP 8-Bit-Wide Data-Transfer Mode (External Clock

Mode, MAX1068 Only)

Figure 16 shows the DSP-interface timing diagram.

Logic low at DSPR on the falling edge of CS enables

DSP interface mode. After the MAX1068 enters DSP

mode, CS can remain low for the duration of the con-

version process and each subsequent conversion.

Drive DSEL low to select the 8-bit data-transfer mode.

A sync pulse from the DSP at DSPR wakes the analog

circuitry and allows SCLK to clock in data (Figure 17).

The frame sync pulse alerts the MAX1068 that incom-

ing data is about to be sent to DIN. Ensure the duty

cycle on SCLK is between 45% and 55% when operat-

ing at 4.8MHz (the maximum clock frequency). For

lower clock frequencies, ensure the minimum high and

low times are at least 93ns. External clock mode con-

versions with SCLK rates less than 125kHz can reduce

accuracy due to leakage of the sampling capacitor.

The input data latches on the falling edge of SCLK. The

command/configuration/control register starts reading

data in on the falling edge of the first SCLK cycle imme-

diately following the falling edge of the frame sync

pulse and ends on the falling edge of the 8th SCLK

cycle. The MAX1068 selects the proper channel for

conversion on the falling edge of the 3rd clock cycle

and begins acquisition. Acquisition continues until the

rising edge of the 7th clock cycle. The MAX1068 sam-

ples the input on the rising edge of the 7th clock cycle.

On the rising edge of the 8th clock cycle, the MAX1068

outputs a frame sync pulse at DSPX. The frame sync

pulse alerts the DSP that the conversion results are

about to be output at DOUT (MSB first) starting on the

rising edge of the 9th clock pulse. To read the entire

conversion results, 16 SCLK cycles are needed. Extra

clock pulses, occuring after the conversion result has

been clocked out, and prior to the next rising edge of

DSPR, cause zeros to be clocked out of DOUT. The

MAX1068 external-clock, DSP 8-bit-wide data-transfer

mode requires 24 clock cycles to complete.

Begin a new conversion by sending a new frame sync

pulse to DSPR followed by new configuration data.

Send the new DSPR pulse immediately after reading

the conversion result to realize maximum throughput.

Sending a new frame sync pulse in the middle of a con-

version immediately aborts the current conversion and

begins a new one. A rising edge on CS in the middle of

a conversion aborts the current conversion and places

the MAX1068 in shutdown.

DSP 16-Bit-Wide Data-Transfer Mode (External

Clock Mode, MAX1068 Only)

Figure 16 shows the DSP-interface timing diagram. Logic

low at DSPR on the falling edge of CS enables DSP inter-

face mode. After the MAX1068 enters DSP mode, CS

can remain low for the duration of the conversion

process and each subsequent conversion. The acquisi-

tion time is extended an extra eight SCLK cycles in the

16-bit-wide data-transfer mode. Drive DSEL high to

select the 16-bit-wide data-transfer mode. A sync pulse

from the DSP at DSPR wakes the analog circuitry and

allows SCLK to clock in data (Figure 18). The frame

sync pulse also alerts the MAX1068 that incoming data

is about to be sent to DIN. Ensure the duty cycle on

SCLK is between 45% and 55% when operating at

MAX1067/MAX1068

Multichannel, 14-Bit, 200ksps Analog-to-Digital

Converters

______________________________________________________________________________________ 21

SCLK

DSPR

DIN

DOUT

CSS

FSH

CSH

CSW

FSS

...

Figure 16. Detailed DSP-Interface Timing (MAX1068 Only)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

MAX1068CCEG+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps

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MAX1068CCEG+

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