MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 25
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1067/MAX1068 support a
maximum f
SCLK
of 4.8MHz. Figure 21a shows the
MAX1067/MAX1068 connected to a QSPI master and
Figure 21b shows the associated interface timing.
PIC16 with SSP Module and PIC17
Interface
The MAX1067/MAX1068 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
be synchronously transmitted and received simultane-
ously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 14-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the µC on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
2016
D13 D12 D11
D10 D9 D8 D7
HIGH-Z
S1
S0
24
1214 86
D6 D3
D2 D1
LSB
D5 D4
SAMPLING INSTANT
D0
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detection Bit
SSPEN BIT5 1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial
port pins.
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM3 BIT3 0
SSPM2 BIT2 0
SSPM1 BIT1 0
SSPM0 BIT0 1
Synchronous Serial-Port Mode Select Bit. Sets SPI master-mode and
selects f
CLK
= f
OSC
/ 16.
Table 7. Detailed SSPCON Register Contents
X = Don’t care.
QSPI
SCLK
DOUT
CS
SCK
MISO
V
DD
SS
CS
MAX1067
MAX1068
Figure 21a. QSPI Connections
DSP Interface
The DSP mode of the MAX1068 only operates in exter-
nal clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1068. Use the same oscillator as
the DSP to provide the clock signal for the MAX1068.
The DSP provides the falling edge at CS to wake the
MAX1068. The MAX1068 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1068 in DSP mode. After the MAX1068
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1068 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1068 does not
operate in scan mode when using DSP mode.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
26 ______________________________________________________________________________________
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
S1 S0D5 D4 D3 D2 D1 D0
24
20
16128641
D13
D12 D11 D10 D9 D8 D7 D6
00000000
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
V
DD
V
DD
MAX1067
MAX1068
Figure 22a. SPI Interface Connection for a PIC16/PIC17
CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP BIT7 0
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
CKE BIT6 1
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer-Full Status Bit
Table 8. Detailed SSPSTAT Register Contents
X = Don’t care.
MAX1067/MAX1068
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 27
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1067/MAX1068
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of ±1 LSB. A
DNL error specification of ±1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between samples. Aperture delay (t
AD
) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
SNR = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 log [Signal
RMS
/ (Noise +
Distortion)
RMS
]
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Figure 24 shows the ENOB as a function of the MAX1067/
MAX1068s’ input frequency.
DSP
EXTERNAL
CLOCK
SCLK
DSPR
DSPX
DIN
DOUT
SCLK
TFS
RFS
DT
DR
FL1
CS
MAX1068
Figure 23. DSP Interface Connection
0.1 10 100
FREQUENCY (kHz)
EFFECTIVE BITS
1
14
16
0
2
4
6
8
12
10
f
SAMPLE
= 200ksps
EFFECTIVE NUMBER OF BITS (ENOB)
Figure 24. Effective Bits vs. Frequency

MAX1068CCEG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps
Lifecycle:
New from this manufacturer.
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