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9LPRS477CKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
13
SMBus Table: CPU PLL Frequency Control Register
Byte 17 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBus Table: SB_SRC PLL Spread Spectrum Control Register
Byte 18 Name Control Function Type 0 1 Default
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
SMBus Table: SB_SRC PLL Spread Spectrum Control Register
Byte 19 Name Control Function Type 0 1 Default
Bit 7
SSP15 RW X
Bit 6
SSP14 RW X
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
SMBUS Table: CPU Output Divider Register
Byte 20 Name Control Function Type 0 1 Default
Bit 7
CPU NDiv0 LSB N Divider Programming RW X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
CPUDiv3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X
Bit 2
CPUDiv2 RW 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 X
Bit 1
CPUDiv1 RW 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 X
Bit 0
CPUDiv0 RW 0011:/9 ; 0111:/18 1011:/36 ; 1111:/72 X
SMBUS Table: SRC Frequency Control Register
Byte 21 Name Control Function Type 0 1 Default
Bit 7
N Div2 N Divider Prog bit 2 RW X
Bit 6
N Div1 N Divider Prog bit 1 RW X
Bit 5
M Div 5 RW X
Bit 4
M Div 4 RW X
Bit 3
M Div 3 RW X
Bit 2
M Div 2 RW X
Bit 1
M Div 1 RW X
Bit 0
M Div 0 RW X
SMBUS Table: SRC Frequency Control Register
Byte 22 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
Res er v ed
N Divider Programming Byte16
bit(7:0) and Byte15 bit(7:6)
The decimal representation of M and N Divider in Byte 16 and 17
w ill conf igure the VCO frequency. Default at pow er up = Byte
3 Rom table. See M/N Caculation Tables f or VCO frequency
formulas.
M Divider Programming
bit (5:0)
The decimal representation of M and N Divider in Byte 21 and 22
configure the SRC VCO frequency. See M/N Caculation Tables
for VCO frequency formulas.
Byte 28 has the N Divider LSB (bit 0) for CPU M/N programming.
CPU Divider Ratio Programming Bits
The decimal representation of M and N Divider in Byte 21 and 22
configure the SRC VCO frequency. See M/N Caculation Tables
for VCO frequency formulas.
N Divider Programming b(10:3)
These bits set the SB_SRC spread pecentage.Please contact
IDT for the appropriate values.
Spread Spectrum Programming
b(7:0)
Spread Spectrum Programming
b(15:8)
These bits set the SB_SRC spread pecentage.Please contact
IDT for the appropriate values.
Res er v ed
Res er v ed
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
14
SMBUS Table: SRC Spread Spectrum Control Register
Byte 23 Name Control Function Type 0 1 Default
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
SMBUS Table: SRC Spread Spectrum Control Register
Byte 24 Name Control Function Type 0 1 Default
Bit 7
SSP15 RW X
Bit 6
SSP14 RW X
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
SMBUS Table: SRC Output Divider Control Register
Byte 25 Name Control Function Type 0 1 Default
Bit 7
SB_SRC NDiv 0 LSB N Divider Progr amming RW X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
SRCDiv3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X
Bit 2
SRCDiv2 RW 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 X
Bit 1
SRCDiv1 RW 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 X
Bit 0
SRCDiv0 RW 0011:/9 ; 0111:/18 1011:/36 ; 1111:/72 X
SMBUS Table: ATIG Frequency Control Register
Byte 26 Name Control Function Type 0 1 Default
Bit 7
N Div 2 N Div ider Pr og bit 2 RW X
Bit 6
N Div 1 N Div ider Pr og bit 1 RW X
Bit 5
M Div 5 RW X
Bit 4
M Div 4 RW X
Bit 3
M Div 3 RW X
Bit 2
M Div 2 RW X
Bit 1
M Div 1 RW X
Bit 0
M Div 0 RW X
SMBUS Table: ATIG Frequency Control Register
Byte 27 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SRC Divider Ratio Programming Bits
N Div ider Pr ogr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 26 and 27
w ill configure the VCO f requency. Default at pow er up = Byte
5 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
M Divider Programming
bit (5:0)
Res er v ed
Spread Spectrum Programming
bit(7:0)
The decimal representation of M and N Divider in Byte 26 and 27
w ill configure the VCO f requency. Default at pow er up = Byte
5 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
Res er v ed
These bits set the SRC spread pecentages.Please contact IDT
for the appropriate values.
Spread Spectrum Programming
bit(15:8)
These bits set the SRC spread pecentages.Please contact IDT
for the appropriate values.
N Div ider LSB ( bit 0) f or SRC M/N pr ogramming.
Res er v ed
IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
15
SMBUS Table: ATIG Output Divider Control Register
Byte 28 Name Control Function Type 0 1 Default
Bit 7
A TIG NDiv 0 LSB N Div ider Progr amming RW X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
ATIGDiv3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X
Bit 2
ATIGDiv2 RW 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 X
Bit 1
ATIGDiv1 RW 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 X
Bit 0
ATIGDiv0 RW 0011:/9 ; 0111:/18 1011:/36 ; 1111:/72 X
SMBUS Table: SB_SRC Frequency Control Register
Byte 29 Name Control Function Type 0 1 Default
Bit 7
N Div 2 N Div ider Pr og bit 2 RW X
Bit 6
N Div 1 N Div ider Pr og bit 1 RW X
Bit 5
M Div 5 RW X
Bit 4
M Div 4 RW X
Bit 3
M Div 3 RW X
Bit 2
M Div 2 RW X
Bit 1
M Div 1 RW X
Bit 0
M Div 0 RW X
SMBUS Table: SB_SRC Frequency Control Register
Byte 30 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: SB_SRC Output Divider Control Register
Byte 31 Name Control Function Type 0 1 Default
Bit 7
SB_SRC NDiv 0 LSB N Divider Progr amming RW X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
SB_SRCDiv 3 RW 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 X
Bit 2
SB_SRCDiv 2 RW 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 X
Bit 1
SB_SRCDiv 1 RW 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 X
Bit 0
SB_SRCDiv 0 RW 0011:/9 ; 0111:/18 1011:/36 ; 1111:/72 X
SMBUS Table: CPU PLL DOC 1 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 01)
Byte 32 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
SMBUS Table: CPU PLL DOC 2 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 10)
Byte 33 Name Control Function Type 0 1 Default
Bit 7
N Div 10 RW X
Bit 6
N Div 9 RW X
Bit 5
N Div 8 RW X
Bit 4
N Div 7 RW X
Bit 3
N Div 6 RW X
Bit 2
N Div 5 RW X
Bit 1
N Div 4 RW X
Bit 0
N Div 3 RW X
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 16 and 33
w ill configure the VCO f requency. Default at pow er up = Byte
3 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
The decimal representation of M and N Divider in Byte 16 and 32
w ill configure the VCO f requency. Default at pow er up = Byte
3 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
SB_SRC Divider Ratio Programming
Bits
Res er v ed
N Div ider Progr amming By te20
bit(7:0) and Byte19 bit(7:6)
Res er v ed
Res er v ed
M Divider Programming
bit (5:0)
Res er v ed
The decimal representation of M and N Divider in Byte 29 and 30
w ill configure the VCO f requency. Default at pow er up = Byte
6 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
Res er v ed
ATIG Divider Ratio Programming
Bits
N Divider LSB (bit 0) for ATIG M/N programming.
The decimal representation of M and N Divider in Byte 29 and 30
w ill configure the VCO f requency. Default at pow er up = Byte
6 Rom table. See M/N Caculation Tables for VCO frequency
formulas.
Res er v ed
N Div ider LSB ( bit 0) f or SRC M/N pr ogr amming.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

9LPRS477CKLF

Mfr. #:
Buy 9LPRS477CKLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Program Syst CLK ATI RS790 - K8
Lifecycle:
New from this manufacturer.
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