IDT
®
Programmable System Clock Chip for ATI RD790-K8
TM
Based Systems 1393—01/28/14
9LPRS477C
Programmable System Clock Chip for ATI RD790 - K8
TM
based Systems
20
AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC, ATIG
PA RA METER SY MBOL CONDITIONS MIN TY P MA X UNITS NOTES
Rising Edge Slew Rate t
SLR
Differential Measurement 0.6 4 V/ns 1,2
Falling Edge Slew Rate t
FLR
Differential Measurement 0.6 4 V/ns 1,2
Slew Rate Variation t
SLVAR
Single-ended Measurement 20 % 1
Max imum Ou tp ut V oltage V
HIGH
Includes overshoot 1150 mV 1
Min imum Out put V olt ag e V
LOW
Includes undershoot -300 mV 1
Differential Voltage Sw ing V
SWING
Differential Measurement 300 mV 1
Crossing Point Voltage V
XABS
Single-ended Measurement 300 550 mV 1,3,4
Crossing Point Variation V
XABSVAR
Single-ended Measurement 140 mV 1,3,5
Duty Cy c le D
CYC
Differential Measurement 45 55 % 1
SRC, SB_SRC, ATIG,
Jitter - Cycle to Cycle
SRCJ
C2C
Differential Measurement 125 ps 1
SRC[5:0] Skew SRC
SKEW
Differential Measurement 250 ps 1
SB_SRC[1:0] Skew SRC
SKEW
Differential Measurement 100 ps 1
ATIG[3:0] Skew SRC
SKEW
Differential Measurement 100 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 2pF w ith Rs = 0Ω (unless otherw ise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vsw ing centered around differential zero
3
Vxabs is def ined as the voltage w here CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
6
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
5
Def ined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
f alling edge of CLK#. It is measured using a +/-75mV w indow centered on the average cross point w here CLK meets CLK#.
PA RA METER SY MBOL CONDITIONS MIN TY P MA X UNITS Notes
Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2
33.33MHz output nominal 29.9910 30.0090 ns 2
33.33MHz output spread 29.9910 30.1598 ns 2
66.67MHz output nominal 14.9955 15.0045 ns 2
66.67MHz output spread 14.9955 15.0799 ns 2
Output High Voltage V
OH
I
OH
= -1 mA 2.4 V 1
Output Low Voltage V
OL
I
OL
= 1 mA 0.55 V 1
V
OH
@MIN = 1.0 V -33 mA 1
V
OH
@ MAX = 3.135 V -33 mA 1
V
OL
@ MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V 38 mA 1
Edge Rate
V
t Rising edge rate 1 4 V/ns 1
Edge Rate
V
t Falling edge rate 1 4 V/ns 1
Ris e Time t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V 0.5 2 ns 1
Fall Time t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V 0.5 2 ns 1
Duty Cy c le d
t1
V
T
= 1.5 V 45 55 % 1
Jitter, Cycle to cycle t
j c yc-c yc
V
T
= 1.5 V 180 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5pF w ith Rs = 33Ω (unless otherw ise specif ied)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed w ith the assumption that REF is at 14.31818MHz
I
OH
Electrical Characteristics - Single-Ended HTT 66MHz Clock
PCI33 Clock period
HTT66 Clock period
T
period
T
period
Output High Current
I
OL
Output Low Current
