Data Sheet ADL5303
Rev. A | Page 15 of 24
LOW SUPPLY SLOPE AND INTERCEPT
ADJUSTMENT
When using the device with a supply of less than 4 V, it is
necessary to reduce the slope and intercept at the VLOG pin
to preserve good log conformance over the entire 160 dB oper-
ating range. The voltage at the VLOG pin is generated by an
internal current source with an output current of 40 μA/decade
feeding the internal laser trimmed output resistance of 5 kΩ.
When the voltage at the VLOG pin exceeds V
P
2.3 V, the
current source ceases to respond linearly to logarithmic
increases in current. Avoid headroom issues by reducing
the logarithmic slope and intercept at the VLOG pin and by
connecting an external resistor, R
S
, from the VLOG pin to
ground in combination with an intercept lowering resistor, R
Z
.
The values shown in Figure 28 illustrate a good solution for a
3.0 V positive supply. The resulting logarithmic slope measured
at VLOG is 62.5 mV/decade with a new intercept of 57 fA. The
original logarithmic slope of 200 mV/decade can be recovered
using voltage gain on the internal buffer amplifier.
CHANGING THE VOLTAGE AT THE SUMMING NODE
The default value of VSUM is determined by using a quarter
of VREF (2 V). This can be altered by applying an independent
voltage source to VSUM, or by adding an external resistive
divider from VREF to VSUM. This network operates in parallel
with the internal divider (40 kΩ and 13.3 kΩ), and the choice
of external resistors should take this into account. In practice,
the total resistance of the added string may be as low as 10 kΩ
(consuming 400 μA from VREF). Low values of VSUM and
thus V
CE
are not advised when large values of I
PD
are expected.
NC
V
OUT
500mV/DEC
R18 (R
B
)
C7 (R
S
)
2.67k
R14 (R
Z
)
15.4kΩ
R15 (R
A
)
4.98k
2.26k
NC = NO CONNECT
V
P
100nF
R1
750
C1
1nF
I
PD
C3
PDB BIAS
VREF
VPDB
VSUM
INPT
VSUM
ACOM
VPS2
PWDN VPS1
VREF
VLOG
BFIN
BFNG
VOUT
0.5V
ADL5303
~10k
5kΩ
5
2
3
4
15 14
GNDGND
7 11
10
16
12
6
8
9
13
TEMPERATURE
COMPENSATION
10661-028
Figure 28. Recommended Low Supply Application Circuit
ADL5303 Data Sheet
Rev. A | Page 16 of 24
USING THE ADAPTIVE BIAS
For most photodiode applications, the placement of the anode
somewhat above ground is acceptable, as long as the positive
bias on the cathode is adequate to support the peak current for
a particular diode, limited mainly by its series resistance. To
address this matter, the ADL5303 provides for a diode bias that
increases linearly with the current. This bias voltage appears at
the VPDB pin, and varies from 0.6 V (reverse-biasing the diode
by 0.1 V) for I
PD
= 100 pA and rises to 2.6 V (for a diode bias of
2 V) at I
PD
= 10 mA. This results in a constant internal junction
bias of 0.1 V when the series resistance of the photodiode is
200 Ω. For optical power measurements over a wide dynamic
range, the adaptive biasing function is valuable in minimizing
dark current while preventing the loss of photodiode bias at
high currents. Use of the adaptive bias feature is shown in
Figure 29.
Capacitor CPB, between the photodiode cathode at the VPDB
pin and ground, is included to lower the impedance at this node
and thereby improve the high frequency accuracy at current
levels where the ADL5303 bandwidth is high. CPB also ensures
a high frequency path for any high frequency modulation on
the optical signal, which might not otherwise be accurately
averaged. CPB is not necessary in all cases, and experimentation
may be required to find an optimum value.
NC
V
OUT
500mV/DEC
R18 (R
B
)
C7 (C
FILT
)
R15 (R
A
)
15k
10k
NC = NO CONNECT
V
P
100nF
R1
750
C1
1nF
CPB
R25
I
PD
C3
PDB
BIAS
VREF
VPDB
LOCATION
VSUM
INPT
VSUM
ACOM
VPS2
PWDN
VPS1
VREF
VLOG
BFIN
BFNG
VOUT
0.5V
ADL5303
~10k
5k
5
2
3
4
15 14
GND
GND
7 11
10
16
12
6
8
9
13
TEMPERATURE
COMPENSATION
10661-029
Figure 29. Using the Adaptive Biasing
Data Sheet ADL5303
Rev. A | Page 17 of 24
APPLICATIONS INFORMATION
Smaller input voltages can be measured accurately when
aided by a small offset nulling voltage applied to VSUM.
The minimum voltage that can be accurately measured is
limited only by the drift in the input offset of the ADL5303.
The specifications show the maximum spread over the full
temperature and supply range. Over a limited temperature
range and with a regulated supply, the offset drift is lower;
in this situation, processing of inputs down to 5 mV is
practicable.
RESCALING
The use of a much larger value for the intercept may be useful
in certain situations. In this example, it has been moved up four
decades, from the default value of 100 pA to the center of the
full eight-decade range at 1 mA. Using a voltage input as previ-
ously described, this corresponds to an altered voltage mode
intercept, V
Z
, which is 1 V for R
IN
= 1 MΩ. To take full advantage
of the larger output swing, the gain of the buffer has been
increased to 4.53, resulting in a scaling of 900 mV/decade
zand a full-scale output of ±3.6 V.
INVERTING THE SLOPE
The buffer is essentially an uncommitted op amp that can be
used to support the operation of the ADL5303 in a variety of
ways. It can be completely disconnected from the signal chain
when not needed. Figure 30 shows its use as an inverting ampli-
fier; this changes the polarity of the slope. The output can be
repositioned to a positive value by applying a fraction of V
REF
to the BFIN pin. The full design for a practical application is
left undefined in this brief illustration, but a few cases are
discussed, as follows.
For example, if slope of 30 mV/dB is needed; a gain of 3 is
required. Because VLOG exhibits a source resistance of 5 kΩ,
R
A
must be 15 kΩ. A positive offset, V
OS
, is applied to the BFIN
pin, as indicated in Figure 30. The resulting output voltage can
be expressed as
OS
Z
PD
Y
A
OUT
V
I
I
V
R
V
+
×
=
10
log
k
Ω5
(11)
When the gain is set to 13 (R
A
= 5 kΩ), the 2 V V
REF
can be tied
directly to BFIN, in which case the starting point for the output
response is at 4 V. However, because the slope in this case is
only 0.2 V/decade, the full current range takes the output
down by only 1.6 V. Clearly, a higher slope (or gain) is desirable;
in which case, set V
OS
to a smaller voltage to avoid railing the
output at low currents. If V
OS
= 1.2 V and G = 33, VOUT now
starts at 4.8 V and falls through this same voltage toward ground
with a slope of 0.6 V per decade, spanning the full range of I
PD
.
NC
V
OUT
R15 (R
A
)
V
OS
NC
NC = NO CONNECT
V
P
100nF
R1
750
C1
1nF
I
PD
C3
PDB BIAS VREF
VPDB
VSUM
INPT
VSUM
ACOM
VPS2
PWDN VPS1
VREF
VLOG
BFIN
BFNG
VOUT
0.5V
ADL5303
~10k
5k
5
2
3
4
15 14
GNDGND
7 11
10
16
12
6
8
9
13
TEMPERATURE
COMPENSATION
10661-030
Figure 30. Using the Buffer to Invert the Polarity of the Slope

ADL5303ACPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers Log Amp
Lifecycle:
New from this manufacturer.
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