Data Sheet ADL5303
Rev. A | Page 3 of 24
SPECIFICATIONS
V
PS
= 5 V, GND, ACOM = 0 V, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min
1
Typ Max
1
Unit
INPUT INTERFACE Pin 3, INPT; Pin 2 and Pin 4, VSUM
Specified Current Range Flows toward Pin 3 100 pA
10 mA
Input Node Voltage Internally preset; may be altered 0.46 0.5 0.54 V
Temperature Drift 40°C < T
A
< +85°C 0.04 mV/°C
Input Guard Offset Voltage V
OFS
= V
IN
V
SUM
−20 +20 mV
PHOTODIODE BIAS
2
Established between VPDB and INPT
Minimum Value I
PD
= 100 pA 70 100 mV
Transresistance 200 mV/mA
LOGARITHMIC OUTPUT Pin 8, VLOG
Slope Laser trimmed at 25°C 195 200 205 mV/dec
0°C < T
A
< 70°C 193 207 mV/dec
Intercept
60
100
140
pA
0°C < T
A
< 70°C 35 175 pA
Law Conformance Error 10 nA < I
PD
< 1 mA, peak error 0.05 0.25 dB
1 nA < I
PD
< 1 mA, peak error 0.1 0.7 dB
Maximum Output Voltage 1.6 V
Minimum Output Voltage 0.1 V
Output Resistance Laser trimmed at 25°C 4.95 5 5.05 kΩ
REFERENCE OUTPUT Pin 6, VREF
Voltage WRT Ground Laser trimmed at 25°C 1.98 2 2.02 V
40°C < T
A
< +85°C 1.92 2.08 V
Output Resistance 2
OUTPUT BUFFER
Input Offset Voltage −20 +20 mV
Input Bias Current Flowing out of Pin 9 or Pin 13 0.4 μA
Incremental Input Resistance 35 MΩ
Output Range R
L
= 1 kΩ to ground V
PS
− 0.1 V
Output Resistance 0.5
Wideband Noise
3
PD
1
μV/√Hz
Small Signal Bandwidth
3
I
PD
> 1 μA (see the Typical Performance Characteristics section) 10 MHz
Slew Rate 0.2 V to 4.8 V output swing 15 V/μs
POWER-DOWN INPUT Pin 16, PWDN
Logic Level, High State 40°C < T
A
< +85°C, 2.7 V < V
PS
< 5.5 V 2 V
Logic Level, Low State 40°C < T
A
< +85°C, 2.7 V < V
PS
< 5.5 V 1 V
POWER SUPPLY Pin 10 and Pin 12, VPS2 and VPS1; Pin 14 and 15, GND
Supply Voltage 3.0 5 5.5 V
Quiescent Current 4.5 5.6 mA
In Disabled State 60 μA
1
Minimum and maximum specified limits on parameters are guaranteed but not tested and are six sigma values.
2
This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.
3
Output noise and incremental bandwidth are functions of input current; see the Typical Performance Characteristics section.
ADL5303 Data Sheet
Rev. A | Page 4 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
V
PS
6 V
Input Current to INPT 20 mA
Thermal Data, 2-Layer JEDEC Board, No Air
Flow (Exposed Pad Soldered to PCB)
θ
JA
61.6°C/W
θ
JC
1.2°C/W
Maximum Power Dissipation (Exposed
Pad Soldered to PCB)
0.6 W
Maximum Junction Temperature
125°C
Operating Temperature Range 40°C to +85°C
Storage Temperature Range 65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet ADL5303
Rev. A | Page 5 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT
IT IS BETTER TO CONNECT THESE PINS TO GROUND.
AVOID ROUTING HIGH SPEED SIGNALS THROUGH
THESE PINS BECAUSE NOISE COUPLING MAY RESULT.
2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE
VSUM PINS TO PROVIDE LOW LEAKAGE GUARD.
1NC
2VSUM
3INPT
4VSUM
11 VOUT
12 VPS1
10 VPS2
9 BFIN
5
VPDB
6
VREF
7
ACOM
8
VLOG
15
GND
16
PWDN
14
GND
13
BFNG
ADL5303
TOP VIEW
(Not to Scale)
10661-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC
Pins labeled NC can be allowed to float, but it is better to connect these pins to ground. Avoid routing high
speed signals through these pins because noise coupling may result.
2, 4 VSUM Guard Pins. VSUM is used to shield the INPT current line.
3 INPT Photodiode Current Input. Connect this pin to the photodiode anode (the photo current flows toward INPT).
5
VPDB
Photodiode Biaser Output. Connect this pin to the photodiode cathode when using adaptive bias control;
otherwise, leave this pin floating.
6 VREF Voltage Reference Output of 2 V.
7 ACOM Analog Reference Ground.
8 VLOG Output of the Logarithmic Front-End Processor. R
OUT
= 5 kΩ to ground.
9 BFIN Buffer Amplifier Noninverting Input (High Impedance).
10
VPS2
Positive Supply, V
PS
(3.0 V to 5.5 V).
11 VOUT Buffer Output; Low Impedance.
12 VPS1 Positive Supply, V
PS
(3.0 V to 5.5 V).
13 BFNG Buffer Amplifier Inverting Input.
14, 15 GND Power Supply Ground Connection.
16
PWDN
Power-Down Control Input. Device is active when PWDN is taken low.
17 EPAD Exposed Pad. Connect the exposed pad to the VSUM pins to provide low leakage guard.

ADL5303ACPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Logarithmic Amplifiers Log Amp
Lifecycle:
New from this manufacturer.
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