XRT91L34
16
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
Jitter specification is defined using a 12kHz to 0.4/1.3/5MHz LP-HP single-pole filter.
1
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
rms
).
2
Required to meet SONET output frequency stability requirements.
2.2.1 Internal Clock and Data Recovery Disable
Optionally, each of the four internal CDR unit can be disabled and powered down when the channel is not in
use. Asserting the CDRDISn pin (where n = channel 0, 1, 2, or 3 ) "High" in Hardware Mode or setting
CDRDISn bit (where n = channel 0, 1, 2, or 3 ) in Host Mode, disables the internal Clock and Data Recovery
unit for that particular channel.
2.3 External Receive Loop Filter Capacitors
For STS12/STM4 and STS3/STM1 operation, use 0.47µF (or greater) non-polarized external loop filter
capacitors to achieve the required receiver jitter performance for each of the channels. For STS1/STM0
operation, use a minimum of 1.0µF non-polarized capacitors. If all 3 data rates STS12/STS3/STS1 are
required in an application, then use 1uF loop filter capacitors. They must be well isolated to prohibit noise
entering the CDR block and should be placed as close to the pins as possible. Figure 6 shows the pin
connections and external loop filter components. These four non-polarized capacitors should be of +/- 10%
tolerance. Use type X7R or X5R capacitors for improved stability over temperature.
T
ABLE
3: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
40 60 %
REF
TOL
Reference clock frequency tolerance
2
-100 +100 ppm
TOL
JIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.3 0.4 UI
OCLK
DUTY
Clock output duty cycle
45 55 %
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
CAP1NCAP1P
0.47uF
non-polarized
CAP3NCAP3P
0.47uF
non-polarized
CAP0NCAP0P
0.47uF
non-polarized
Channel 0 Loop Filter
External Capacitor
pin 108
pin 109 pin 103
pin 102
Channel 1 Loop Filter
External Capacitor
CAP2NCAP2P
0.47uF
non-polarized
Channel 2 Loop Filter
External Capacitor
pin 60
pin 59 pin 53
Pin 54
Channel 3 Loop Filter
External Capacitor
Use 1.
.
..
.
0uF non-polarized
capacitors for
STS1/STM0 Operation
XRT91L34
17
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
2.4 Internal Digital Loss of Signal and External Signal Detection
XRT91L34 has an integrated Digital Loss of Signal (DLOS) circuit and supports external Signal Detection
(SDEXT) for detecting and determining received signal integrity. The internal DLOS circuit monitors the
incoming data stream. If the incoming data stream has no transition for more than 2.5µs, Loss of Signal is
declared. This LOS condition will be cleared when the circuit detects transitions in a 128µs interval sliding
window. Pulling the DLOSDIS pin signal to a high level in hardware mode or setting DLOSDIS bit in host mode
will disable the internal DLOS detection circuit to permit the framer/mapper interface to determine the Loss of
Signal declaration and clearance criteria for specific applications. The external Signal Detect function is
supported by the SDEXT input. An LVCMOS/LVTTL signal comes from the optical module through an output
usually called SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices, the polarity of this signal can be either active "Low" or active "High." The
SDEXT and POL inputs are Exclusive OR’ed to determine external Loss of Signal (LOS) condition. In the event
that internal DLOS is detected or an external SDEXT input indicates signal absence, the recovered serial data
output will be forced to a logic state "0," and the LOS status register is set whenever the host mode serial
microprocessor interface is active. This acts as a receive data mute upon LOS function to prevent data
chattering and to prevent random noise from being misinterpreted as valid incoming data. Figure 7 shows the
Loss of Signal Detection logic circuit. Table 4 specifies LOS declaration polarity settings.
F
IGURE
7. L
OSS
OF
S
IGNAL
D
ECLARATION
C
IRCUIT
T
ABLE
4: E
XTERNAL
LOS D
ECLARATION
P
OLARITY
S
ETTING
SDEXT POL I
NTERNAL
S
IGNAL
D
ETECT
LOS
BIT
STATE
(H
OST
MODE
O
NLY
)
RXDO[3:0]P/N
0 0 Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
Low
Normal
Operation
0 1 Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
High
LOS declared
Muted
1 0 Active Low. Optical signal presence
indicated by SDEXT logic 0 input from
optical module.
High
LOS declared
Muted
1 1 Active High. Optical signal presence
indicated by SDEXT logic 1 input from
optical module.
Low
Normal
Operation
DLOSDIS
(Internal) DLOS Detect
(External) SDEXT
LOS Declaration
POL
and
Recovered Data Mute
XRT91L34
18
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
2.5 Multichannel Recovered Output Interface
The recovered data RXDO[3:0]P/N differential output drivers along with the recovered clock RXCLKO[3:0]P/N
differential output drivers can be configured for LVDS or Differential LVPECL standard operation. In addition,
Host Mode operation permits each of the channelized recovered clock output to be independently disabled
such as in repeater applications to save power.
F
IGURE
8. M
ULTICHANNEL
R
ECOVERED
O
UTPUT
I
NTERFACE
B
LOCK
OUTCFG = 0
RXDO0P
RXDO0N
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
Channel 0
Channel 1
Channel 2
Channel 3
LVDS Operation
100
100
100
100
Internal or External 100 Ohm
line-to-line termination required on
RXDO[3:0]P and RXDO[3:0]N pins
on the SONET Framer/ASIC end
SONET Framer/
ASIC
RXCLKO[3:0]P and
RXCLKO[3:0]N
Clock Output pins
terminated similarly
RXDO0P
RXDO0N
XRT91L34
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
Channel 0
Channel 1
Channel 2
Channel 3
LVPECL Operation
SONET Framer/
ASIC
82 x 8
Install terminators as close to
SONET Framer/ ASIC pins
120 x 8
VDD
IO
RXCLKO[3:0]P and
RXCLKO[3:0]N
Clock Output pins
terminated similarly
OUTCFG = 1

XRT91L34IV-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
Telecom Interface ICs 8-Bit TTL 1.8V temp -45 to 85C;UART
Lifecycle:
New from this manufacturer.
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