XRT91L34
IV
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L34 ...................................................................................................................................... 1
APPLICATIONS...........................................................................................................................................2
FEATURES
......................................................................................................................................................2
F
IGURE
2. 128 LQFP P
IN
O
UT
OF
THE
XRT91L34 (T
OP
V
IEW
)........................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3
T
ABLE
OF
C
ONTENTS
..........................................................................................................
IV
PIN DESCRIPTIONS ..........................................................................................................6
H
ARDWARE
C
ONTROL
....................................................................................................................................6
R
ECEIVER
S
ECTION
........................................................................................................................................9
P
OWER
AND
G
ROUND
..................................................................................................................................10
SERIAL
M
ICROPROCESSOR
INTERFACE......................................................................................................11
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12
1.2 STS-12/STM-4 AND STS-3/STM-1 AND STS-1/STM-0 MODE OF OPERATION ......................................... 12
T
ABLE
1: C
HANNEL
D
ATA
R
ATE
S
ELECTION
.................................................................................................................................... 12
1.3 REFERENCE CLOCK INPUT ......................................................................................................................... 13
T
ABLE
2: CDR R
EFERENCE
F
REQUENCY
O
PTIONS
(LVDS/ D
IFF
LVPECL
OR
S
INGLE
-E
NDED
LVTTL/LVCMOS)............................ 13
F
IGURE
3. R
EFERENCE
C
LOCK
D
ESIGN
O
PTIONS
............................................................................................................................ 13
2.0 RECEIVE SECTION .............................................................................................................................14
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 14
F
IGURE
4. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
USING
LVDS/D
IFF
LVPECL DC
COUPLING
INTERNAL
TERM
....................................... 14
F
IGURE
5. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
USING
D
IFF
LVPECL AC
COUPLING
INTERNAL
TERMINATION
..................................... 15
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 15
T
ABLE
3: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 16
2.2.1 INTERNAL CLOCK AND DATA RECOVERY DISABLE ........................................................................................... 16
2.3 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 16
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 16
2.4 INTERNAL DIGITAL LOSS OF SIGNAL AND EXTERNAL SIGNAL DETECTION ...................................... 17
F
IGURE
7. L
OSS
OF
S
IGNAL
D
ECLARATION
C
IRCUIT
........................................................................................................................ 17
T
ABLE
4: E
XTERNAL
LOS D
ECLARATION
P
OLARITY
S
ETTING
........................................................................................................... 17
2.5 MULTICHANNEL RECOVERED OUTPUT INTERFACE ............................................................................... 18
F
IGURE
8. M
ULTICHANNEL
R
ECOVERED
O
UTPUT
I
NTERFACE
B
LOCK
................................................................................................ 18
2.6 DIFFERENTIAL RECOVERED DATA OUTPUT TIMING ............................................................................... 19
F
IGURE
9. D
IFFERENTIAL
R
ECOVERED
O
UTPUT
T
IMING
................................................................................................................... 19
T
ABLE
5: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
).................................................................................... 19
T
ABLE
6: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
)...................................................................................... 19
T
ABLE
7: R
ECOVERED
D
ATA
O
UTPUT
T
IMING
(STS-1/STM-0 O
PERATION
)...................................................................................... 19
3.0 JITTER PERFORMANCE ....................................................................................................................20
3.1 SONET JITTER REQUIREMENTS ................................................................................................................. 20
3.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 20
F
IGURE
10. GR-253/G.783 J
ITTER
T
OLERANCE
M
ASK
................................................................................................................... 20
F
IGURE
11. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
51.84 M
BPS
STS-1/STM-0.................................................................. 20
F
IGURE
12. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
155.52 M
BPS
STS-3/STM-1................................................................ 21
F
IGURE
13. XRT91L34 M
EASURED
J
ITTER
T
OLERANCE
AT
622.08 M
BPS
STS-12/STM-4.............................................................. 21
3.1.2 RX JITTER TRANSFER .............................................................................................................................................. 22
F
IGURE
14. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
51.84 M
BPS
STS-1/STM-0.................................................................... 22
F
IGURE
15. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
155.52 M
BPS
STS-3/STM-1.................................................................. 22
F
IGURE
16. XRT91L34 M
EASURED
J
ITTER
T
RANSFER
AT
622.08 M
BPS
STS-12/STM-4................................................................ 23
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK ..........................................................................24
F
IGURE
17. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 24
4.1 SERIAL TIMING INFORMATION .................................................................................................................... 24
F
IGURE
18. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 24
4.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 25
4.2.1 R/W (SCLK1)............................................................................................................................................................... 25
4.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 25
4.2.3 X (DUMMY BIT SCLK8) .............................................................................................................................................. 25
4.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 25
4.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 25
