XRT91L34
28
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
T
ABLE
10: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
01
B
IT
D
ESCRIPTION
CHANNEL INTERRUPT STATUS REGISTER (0X01)
BIT NAME FUNCTION
Regis-
ter
Type
Default
Value
(HW Reset)
D7 Reserved This Register Bit is Not Used RO 0
D6 Reserved This Register Bit is Not Used RO 0
D5 Reserved This Register Bit is Not Used RO 0
D4 Reserved This Register Bit is Not Used RO 0
D3 INTS3 Channel 3 Interrupt Status
This bit indicates an interrupt occuring in Channel 3.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
D2 INTS2 Channel 2 Interrupt Status
This bit indicates an interrupt occuring in Channel 2.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
D1 INTS1 Channel 1 Interrupt Status
This bit indicates an interrupt occuring in Channel 1.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
D0 INTS0 Channel 0 Interrupt Status
This bit indicates an interrupt occuring in Channel 0.
"0" = No Interrupt Generated
"1" = Channel Interrupt Occurring
RO 0
T
ABLE
11: M
ICROPROCESSOR
I
NTERFACE
R
EGISTER
0
X
02 B
IT
D
ESCRIPTION
DEVICE "ID" REGISTER (0X02)
BIT NAME FUNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Device "ID"
MSB
The device "ID" of the XRT91L34 CDR is 0x8405h. Along with the
revision "ID", the device "ID" is used to enable software to identify
the silicon adding flexibility for system control and debug.
RO 1
0
0
0
0
1
0
0
