ADN2804ACPZ-RL7 Datasheet ADN2804ACPZ-RL7, ADN2804ACPZ-500RL7, ADN2804ACPZ | P19-P21

ADN2804 Data Sheet

Rev. D | Page 18 of 24

To control the device on the bus, the following protocol must be

followed. First, the master initiates a data transfer by establish-

ing a start condition, defined by a high-to-low transition on

SDA while SCK remains high. This indicates that an address/

data stream follows. All peripherals respond to the start condition

and shift the next eight bits (the 7-bit address and the R/W bit).

The bits are transferred from MSB to LSB. The peripheral that

recognizes the transmitted address responds by pulling the data

line low during the ninth clock pulse. This is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is

where the device monitors the SDA and SCK lines, waiting for

the start condition and correct transmitted address. The R/W

bit determines the direction of the data. Logic 0 on the LSB of

the first byte means that the master writes information to the

peripheral. Logic 1 on the LSB of the first byte means that the

master reads information from the peripheral.

The ADN2804 acts as a standard slave device on the bus. The data

on the SDA pin is eight bits long, supporting the 7-bit addresses

plus the R/W bit. The ADN2804 has eight subaddresses to enable

the user-accessible internal registers (see Table 6 through

Table 10). It, therefore, interprets the first byte as the device

address and the second byte as the starting subaddress. Auto-

increment mode is supported, allowing data to be read from or

written to the starting subaddress and each subsequent address

without manually addressing the subsequent subaddress. A data

transfer is always terminated by a stop condition. The user can

also access any unique subaddress register on a one-by-one

basis without updating all registers.

Stop and start conditions can be detected at any stage of the

data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCK high period, the

user should issue one start condition, one stop condition, or a

single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADN2804 does not

issue an acknowledge and returns to the idle condition. If the

user exceeds the highest subaddress while reading back in auto-

increment mode, then the highest subaddress register contents

continue to be output until the master device issues a no acknow-

ledge. This indicates the end of a read. In a no-acknowledge

condition, the SDATA line is not pulled low on the ninth pulse.

See Figure 8 and Figure 9 for sample write and read data transfers

and Figure 10 for a more detailed timing diagram.

Additional Features Available via the I

C Interface

LOS Configuration

The LOS detector output, Pin 22, can be configured to be either

active high or active low. If CTRLC[2] is set to Logic 0 (default),

the LOS pin is active high when a loss-of-signal condition is

detected. Writing a 1 to CTRLC[2] configures the LOS pin to be

active low when a loss-of-signal condition is detected.

System Reset

A frequency acquisition can be initiated by writing a 1 followed

by a 0 to the I

C Register Bit CTRLB[5]. This initiates a new

frequency acquisition while keeping the ADN2804 in its

previously programmed operating mode, as set in Registers

CTRL[A], CTRL[B], and CTRL[C].

Data Sheet ADN2804

Rev. D | Page 19 of 24

REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data

recovery with the ADN2804; however, support for an optional

reference clock is provided. The reference clock can be driven

differentially or in a single-ended fashion. If the reference

clock is not being used, REFCLKP should be tied to VCC,

and REFCLKN can be left floating or tied to VEE (the inputs

are internally terminated to VCC/2). See Figure 21 through

Figure 23 for sample configurations.

The REFCLK input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV (for

example, LVPECL or LVDS) or a standard single-ended, low

voltage TTL input, providing maximum system flexibility.

Phase noise and duty cycle of the reference clock are not

critical, and 100 ppm accuracy is sufficient.

100kΩ

VCC/2

100kΩ

ADN2804

REFCLKP

REFCLKN

BUFFER

5801-021

Figure 21. Differential REFCLK Configuration

100kΩ

VCC/2

100kΩ

ADN2804

REFCLKP

OUT

REFCLKN

BUFFER

CLK

OSC

5801-022

Figure 22. Single-Ended REFCLK Configuration

100kΩ

VCC/2

100kΩ

ADN2804

REFCLKP

REFCLKN

BUFFER

VCC

5801-023

Figure 23. No REFCLK Configuration

There are two mutually exclusive uses, or modes, of the

reference clock. The reference clock can be used either to help

the ADN2804 lock onto data or to measure the frequency of the

incoming data to within 0.01%. The modes are mutually

exclusive because in the first use the user knows exactly what

the data rate is and wants to force the part to lock onto only that

data rate, and in the second use the user does not know what

the data rate is and wants to measure it.

Lock-to-reference mode is enabled by writing a 1 to I

C Register

Bit CTRLA[0]. Fine data rate readback mode is enabled by

writing a 1 to I

C Register Bit CTRLA[1]. Writing a 1 to both of

these bits at the same time causes an indeterminate state and is

not supported.

Using the Reference Clock to Lock onto Data

In this mode, the ADN2804 locks onto a frequency derived

from the reference clock according to

Data Rate/2

CTRLA[5:2]

= REFCLK/2

CTRLA[7, 6]

The user must provide a reference clock that is a function of the

data rate. By default, the ADN2804 expects a reference clock of

19.44 MHz. Other options are 38.88 MHz, 77.76 MHz, and

155.52 MHz, which are selected by programming CTRLA[7, 6].

CTRLA[5:2] should be programmed to [0101] for all cases.

Table 11. CTRLA Settings

CTRLA[7, 6] Range (MHz) CTRLA[5:2] Ratio

00 19.44 0101 2

01 38.88 0101 2

10 77.76 0101 2

11 155.52 0101 2

For example, if the reference clock frequency is 38.88 MHz and the

input data rate is 622.08 Mbps, CTRLA[7, 6] is set to [01] to

produce a divided-down reference clock of 19.44 MHz, and

CTRLA[5:2] is set to [0101], that is, 5, because

622.08 Mbps/19.44 MHz = 2

In this mode, if the ADN2804 loses lock for any reason, it relocks

onto the reference clock and continues to output a stable clock.

While the ADN2804 is operating in lock-to-reference mode,

a 0 to 1 transition should be written into the CTRLA[0] bit to

initiate a lock-to-reference clock command.

ADN2804 Data Sheet

Rev. D | Page 20 of 24

Using the Reference Clock to Measure Data Frequency

The user can also provide a reference clock to measure the

recovered data frequency. In this case, the user provides a

reference clock, and the ADN2804 compares the frequency of

the incoming data to the incoming reference clock and returns a

ratio of the two frequencies to within 0.01% (100 ppm) accuracy.

The accuracy error of the reference clock is added to the accuracy

of the ADN2804 data rate measurement. For example, if a 100 ppm

accuracy reference clock is used, the total accuracy of the measure-

ment is within 200 ppm.

The reference clock can range from 10 MHz to 160 MHz.

By default, the ADN2804 expects a reference clock between

10 MHz and 20 MHz. If the reference clock is between 20 MHz

and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz,

the user must configure the ADN2804 for the correct reference

frequency range by setting two bits of the CTRLA register,

CTRLA[7, 6]. Using the reference clock to determine the frequency

of the incoming data does not affect the manner in which the

part locks onto data. In this mode, the reference clock is used

only to determine the frequency of the data.

Prior to reading back the data rate using the reference clock, the

CTRLA[7, 6] bits must be set to the appropriate frequency

range with respect to the reference clock being used. A fine data

rate readback is then executed as follows:

1. Write a 1 to CTRLA[1]. This enables the fine data rate

measurement capability of the ADN2804. This bit is level

sensitive and can perform subsequent frequency measurements

without being reset.

2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].

This initiates a new data rate measurement.

3. Read back MISC[2]. If it is 0, the measurement is not

complete. If it is 1, the measurement is complete and the

data rate can be read back on FREQ[22:0]. The time for a

data rate measurement is typically 80 ms.

4. Read back the data rate from FREQ2[6:0], FREQ1[7:0], and

FREQ0[7:0].

The data rate can be determined by

[ ]

( )

)

_14

(

RATE

SEL

REFCLK

DATARATE

fFREQ

where:

FREQ[22:0] is the reading from FREQ2[6:0] (MSB byte,

FREQ1[7:0], and FREQ0[7:0] (LSB byte).

DATA R ATE

is the data rate (Mbps).

REFCLK

is the REFCLK frequency (MHz).

SEL_R AT E is the setting from CTRLA[7, 6].

For example, if the reference clock frequency is 32 MHz,

SEL_RATE = 1, because the reference frequency falls into the

20 MHz to 40 MHz range, setting CTRLA[7, 6] to [01],.

Assume for this example that the input data rate is 622.08 Mb/s

(OC12). After following Step 1 through Step 4, the value that is

read back on FREQ[22:0] = 0x9B851, which is equal to 637 × 10

Plugging this value into the equation yields

637e3 × 32e6/2

(14 + 1)

= 622.08 Mbps

If subsequent frequency measurements are required, CTRLA[1]

should remain set to 1. It does not need to be reset. The

measurement process is reset by writing a 1 followed by a 0 to

CTRLB[3]. This initiates a new data rate measurement. Follow

Step 2 through Step 4 to read back the new data rate.

Note that a data rate readback is valid only if LOL is low. If LOL

is high, the data rate readback is invalid.

Table 12.

D22 D21 ... D17 D16 D15 D14 ... D9 D8 D7 D6 ... D1 D0

FREQ2[6:0] FREQ1[7:0] FREQ0[7:0]

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADN2804ACPZ-RL7

Mfr. #:

Buy ADN2804ACPZ-RL7

Manufacturer:

Analog Devices Inc.

Description:

Timers & Support Products Anyrate 10 Mbps to 2.7Gbps PA/CDR

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ADN2804ACPZ-RL7

ADN2804ACPZ-RL7

Products related to this Datasheet