ADN2804 Data Sheet
Rev. D | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
=
0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage (VCC) 4.2 V
Minimum Input Voltage (All Inputs) VEE 0.4 V
Maximum Input Voltage (All Inputs) VCC + 0.4 V
Maximum Junction Temperature 125°C
Storage Temperature Range 65°C to +150°C
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-lead LFCSP, 4-layer board with exposed paddle soldered to
VEE, θ
JA
= 28°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the
human body and test equipment and can discharge without detection. Although this product features
proprietary E
SD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Data Sheet ADN2804
Rev. D | Page 7 of 24
TIMING CHARACTERISTICS
CLKOUTP
DATAOUTP/
DATAOUTN
T
S
T
H
05801-002
Figure 2. Output Timing
|V
OD
|
V
OH
DIFFERENTIAL CLKOUTP/N, D
A
T
A
OUTP/N
V
OS
V
OL
0
5801-032
Figure 3. Differential Output Specifications
SIMPLIFIED LVDS
OUTPUT STAGE
R
LOAD
100
100
5mA
5mA
V
DIFF
05801-033
Figure 4. Differential Output Stage
ADN2804 Data Sheet
Rev. D | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05801-004
TEST1 1
VCC 2
VREF 3
PIN
1
INDIC
AT
OR
T
O
P
VIEW
(Not to Scale)
24 VCC
23 VEE
22 LOS
21 SD
A
32 TEST2
20 SCK
19 SADDR5
18 VCC
17 VEE
THRADJ 9
REFCLK
P
10
REFCLKN
11
VCC 12
VEE 13
CF2 14
CF1 15
LO
L 16
NIN
4
PIN 5
SLICEP
6
SLICEN 7
VEE 8
31 VCC
30 VEE
29 DAT
AOUTP
28 DAT
AOUTN
27 SQUELCH
26 CLKOUTP
25 CLKOUTN
ADN2804*
*
THERE IS
AN EXPOSED P
AD ON THE BOT
TOM OF
THE
PACKAGE THAT MUST BE CONNECTED
TO GND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 TEST1 Connect to VCC.
2 VCC P Power for Limiting Amplifier, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7 SLICEN AI Differential Slice Level Adjust Input.
8 VEE P GND for Limiting Amplifier, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz.
11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15
CF1
AO
Frequency Loop Capacitor.
16 LOL DO Loss-of-Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I
2
C Clock Input.
21 SDA DI I
2
C Data Input.
22 LOS DO Loss-of-Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I
2
C GND.
24 VCC P Output Buffer, I
2
C Power.
25 CLKOUTN DO Differential Recovered Clock Output. LVDS.
26 CLKOUTP DO Differential Recovered Clock Output. LVDS.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL.
28
DATAOUTN
DO
Differential Recovered Data Output. LVDS.
29 DATAOUTP DO Differential Recovered Data Output. LVDS.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND.
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.

ADN2804ACPZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products Anyrate 10 Mbps to 2.7Gbps PA/CDR
Lifecycle:
New from this manufacturer.
Delivery:
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