Data Sheet ADN2804
Rev. D | Page 3 of 24
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
− 1,
unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
QUANTIZERDC CHARACTERISTICS
Input Voltage Range @ PIN or NIN, dc-coupled 1.8 2.8 V
Peak-to-Peak Differential Input PIN − NIN 2.0 V
Input Common-Mode Level DC-coupled (see Figure 27, Figure 28, and Figure 29) 2.3 2.5 2.8 V
Differential Input Sensitivity 2
23
1 PRBS, ac-coupled,
1
BER = 1 × 10
10
6 3.3 mV p-p
Input Offset 500 µV
Input RMS Noise BER = 1 × 10
10
290 µV rms
QUANTIZERAC CHARACTERISTICS
Data Rate 622 Mbps
Output Clock Range Locked to 622 Mbps input data 622 MHz
S11 @ 622 MHz 15 dB
Input Resistance Differential 100
Input Capacitance 0.65 pF
QUANTIZERSLICE ADJUSTMENT
Gain SLICEP − SLICEN = ±0.5 V 0.10 0.11 0.13 V/V
Differential Control Voltage Input SLICEP − SLICEN −0.95 +0.95 V
Control Voltage Range DC level @ SLICEP or SLICEN VEE 0.95 V
Slice Threshold Offset 1 mV
LOSS-OF-SIGNAL (LOS) DETECT
Loss-of-Signal Detect Range (see Figure 6) R
THRESH
= 0 14.9 16.7 18.4 mV
R
THRESH
= 100 k 2.6 3.5 4.4 mV
Hysteresis (Electrical) OC-12
R
THRESH
= 0 6.2 6.9 7.7 dB
R
THRESH
= 100 k 4.1 6.1 8.1 dB
LOS Assert Time DC-coupled
2
500 ns
LOS Deassert Time DC-coupled
2
400 ns
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert With respect to nominal 1000 ppm
VCO Frequency Error for LOL Deassert
250
ppm
LOL Response Time OC-12 200 µs
ACQUISITION TIME
Lock to Data Mode OC-12 2.0 ms
Optional Lock to REFCLK Mode 20.0 ms
DATA RATE READBACK ACCURACY
Fine Readback In addition to REFCLK accuracy
OC-12 100 ppm
POWER SUPPLY VOLTAGE
3.0
3.3
3.6
V
POWER SUPPLY CURRENT Locked to 622.08 Mbps 128 mA
OPERATING TEMPERATURE RANGE 40 +85 °C
1
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2
When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 input termination of the
ADN2804 input stage.
ADN2804 Data Sheet
Rev. D | Page 4 of 24
JITTER SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
− 1,
unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth OC-12 75 130 kHz
Jitter Peaking OC-12 0 0.03 dB
Jitter Generation OC-12, 12 kHz to 5 MHz 0.001 0.003 UI rms
0.011
0.026
UI p-p
Jitter Tolerance OC-12, 2
23
1 PRBS
30 Hz
1
100 UI p-p
300 Hz
1
44 UI p-p
25 kHz 2.5 UI p-p
250 kHz
1
1.0 UI p-p
1
Jitter tolerance of the ADN2804 at these jitter frequencies is better than what the test equipment is able to measure.
Data Sheet ADN2804
Rev. D | Page 5 of 24
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions Min Typ Max Unit
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High V
OH
(see Figure 3) 1475 mV
Output Voltage Low V
OL
(see Figure 3) 925 mV
Differential Output Swing V
OD
(see Figure 3) 250 320 400 mV
Output Offset Voltage V
OS
(see Figure 3) 1125 1200 1275 mV
Output Impedance Differential 100
LVDS Outputs Timing
Rise Time 20% to 80% 115 220 ps
Fall Time 80% to 20% 115 220 ps
Setup Time T
S
(see Figure 2), OC-12 760 800 840 ps
Hold Time
T
H
(see Figure 2), OC-12
760
800
840
ps
I
2
C INTERFACE DC CHARACTERISTICS LVCMOS
Input High Voltage
V
IH
0.7 VCC
V
Input Low Voltage V
IL
0.3 VCC V
Input Current V
IN
= 0.1 VCC or V
IN
= 0.9 VCC 10.0 +10.0 µA
Output Low Voltage V
OL
, I
OL
= 3.0 mA 0.4 V
I
2
C INTERFACE TIMING See Figure 11
SCK Clock Frequency 400 kHz
SCK Pulse Width High t
HIGH
600 ns
SCK Pulse Width Low t
LOW
1300 ns
Start Condition Hold Time t
HD;STA
600 ns
Start Condition Setup Time t
SU;STA
600 ns
Data Setup Time t
SU;DAT
100 ns
Data Hold Time t
HD ; DAT
300 ns
SCK/SDA Rise/Fall Time T
R
/T
F
20 + 0.1 Cb
1
300 ns
Stop Condition Setup Time t
SU;STO
600 ns
Bus Free Time Between a Stop and a Start
t
BUF
1300
ns
REFCLK CHARACTERISTICS Optional lock to REFCLK mode
Input Voltage Range @ REFCLKP or REFCLKN
V
IL
0 V
V
IH
VCC V
Minimum Differential Input Drive 100 mV p-p
Reference Frequency 10 160 MHz
Required Accuracy 100 ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage V
IH
2.0 V
Input Low Voltage V
IL
0.8 V
Input High Current I
IH
, V
IN
= 2.4 V 5 µA
Input Low Current I
IL
, V
IN
= 0.4 V −5 µA
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage V
OH
, I
OH
= 2.0 mA 2.4 V
Output Low Voltage V
OL
, I
OL
= +2.0 mA 0.4 V
1
Cb = total capacitance of one bus line in picofarads. If used with Hs-mode devices, faster fall times are allowed.

ADN2804ACPZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products Anyrate 10 Mbps to 2.7Gbps PA/CDR
Lifecycle:
New from this manufacturer.
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