MAX7033ETJ+ Datasheet MAX7033EUI+, MAX7033EUI+T, MAX7033ETJ+ | P10-P12

The off-chip inductive degeneration is achieved by

connecting an inductor from LNASRC to AGND. This

inductor sets the real part of the input impedance at

LNAIN, allowing for a more flexible input impedance

match, such as a typical PCB trace antenna. A nominal

value for this inductor with a 50Ω input impedance is

15nH, but is affected by PCB trace.

The LC tank filter connected to LNAOUT comprises L3

and C2 (see the

Typical Application Circuit

). Select L3

and C2 to resonate at the desired RF input frequency.

The resonant frequency is given by:

where:

TOTAL

= L3 + L

PARASITICS

TOTAL

= C2 + C

PARASITICS

and C

PARASITICS

include inductance and

capacitance of the PCB traces, package pins, mixer

input impedance, LNA output impedance, etc. These

parasitics at high frequencies cannot be ignored, and

can have a dramatic effect on the tank filter center fre-

quency. Lab experimentation should be done to opti-

mize the center frequency of the tank.

Automatic Gain Control

When the AC pin is low, the automatic gain-control

(AGC) circuit monitors the RSSI output. As the RSSI

output reaches 1.98V, which corresponds to RF input

level of -62dBm, the AGC switches on the LNA gain

reduction resistor. The resistor reduces the LNA gain

by 35dB, thereby reducing the RSSI output by about

500mV. The LNA resumes high-gain mode when the

RSSI level drops back below 1.39V (approximately

-70dBm at RF input) for 1ms. The AGC has a hysteresis

of 8dB. With the AGC function, the MAX7033 can reli-

ably produce an ASK output for RF input levels up to

0dBm with modulation depth of 18dB.

When the AC pin is high and SHDN goes high, the

AGC circuit is disabled and the LNA is always in high-

gain mode. The AGC function can be resumed by

bringing the AC pin low when SHDN is high.

The MAX7033 features an AGC lock function that is

asserted when the level at the AC pin transitions from

low to high while SHDN is high. Locking the AGC locks

the LNA in the current gain state. As shown in Figure 1,

the AGC lock function can be enabled or disabled as

long as the SHDN pin is high. Changing the state of AC

when SHDN is low has no effect.

Mixer

A unique feature of the MAX7033 is the integrated

image rejection of the mixer. This device eliminates the

need for a costly front-end SAW filter for most applica-

tions. Advantages of not using a SAW filter are

increased sensitivity, simplified antenna matching, less

board space, and lower cost.

The mixer cell is a pair of double balanced mixers that

perform an IQ downconversion of the RF input to the

10.7MHz IF from a low-side injected LO (i.e., f

= f

). The image-rejection circuit then combines these

signals to achieve 44dB of image rejection. Low-side

TOTAL TOTAL

2π

MAX7033

315MHz/433MHz ASK Superheterodyne

Receiver with AGC Lock

10 ______________________________________________________________________________________

AGC

LOCK

AGC

UNLOCK

AGC

LOCK

AGC

UNLOCK

EFFECT

SHDN

AC PIN

EFFECT

AGC ENABLED

AGC

ENABLED

AGC

DISABLED

AGC

DISABLED

Figure 1. AGC Lock Activation Cycles

MAX7033

315MHz/433MHz ASK Superheterodyne

Receiver with AGC Lock

______________________________________________________________________________________ 11

COMPONENT VALUE FOR f

= 433MHz VALUE FOR f

= 315MHz DESCRIPTION

C1 100pF 100pF 5%

C2 2pF 4pF ± 0.1pF

C3 100pF 100pF 5%

C4 100pF 100pF 5%

C5 1500pF 1500pF 10%

C6 220pF 220pF 5%

C7 470pF 470pF 5%

C8 0.47μF 0.47μF 20%

C9 220pF 220pF 10%

C10 0.01μF 0.01μF 20%

C11 0.1μF 0.1μF 20%

C12 15pF 15pF Depends on XTAL

C13 15pF 15pF Depends on XTAL

C14 0.01μF 0.01μF 20%

C15 0.01μF 0.01μF 20%

L1 56nH 120nH 5% or better*

L2 15nH 15nH 5% or better*

L3 15nH 27nH 5% or better*

R1 5.1kΩ 5.1kΩ 5%

R2 Open Open —

R3 Short Short —

X1 (÷64) 6.6128MHz** 4.7547MHz** Crystek or Hong Kong Crystal

X1 (÷32) 13.2256MHz** 9.5094MHz** Crystek or Hong Kong Crystal

Y1 10.7MHz ceramic filter 10.7MHz ceramic filter Murata

injection is required due to the on-chip image-rejection

architecture. The IF output is driven by a source follow-

er biased to create a driving-point impedance of 330Ω;

this provides a good match to the off-chip 330Ω ceram-

ic IF filter.

The IRSEL pin is a logic input that selects one of the

three possible image-rejection frequencies. When V

IRSEL

= 0V, the image rejection is tuned to 315MHz. V

IRSEL

DD5

/2 tunes the image rejection to 375MHz, and V

IRSEL

= V

DD5

tunes the image rejection to 433MHz. The IRSEL

pin is internally set to V

DD5

/2 (image rejection at

375MHz) when it is left unconnected, thereby eliminating

the need for an external V

DD5

/2 voltage.

Phase-Locked Loop

The PLL block contains a phase detector, charge

pump, integrated loop filter, VCO, asynchronous 64x

clock divider, and crystal oscillator driver. Besides the

crystal, this PLL does not require any external compo-

nents. The VCO generates a low-side LO. The relation-

ship between the RF, IF, and crystal frequencies is

given by:

where:

M = 1 (V

XTALSEL

= V

DD5

) or 2 (V

XTALSEL

= 0V)

To allow the smallest possible IF bandwidth (for best sen-

sitivity), minimize the tolerance of the reference crystal.

XTAL

RF IF

Table 1. Component Values for Typical Application Circuit

Wire wound recommended.

Crystal frequencies shown are for ÷64 (V

XTALSEL

= 0V) and ÷32 (V

XTALSEL

= V

)

Intermediate Frequency and RSSI

The IF section presents a differential 330Ω load to pro-

vide matching for the off-chip ceramic filter. The six

internal AC-coupled limiting amplifiers produce an

overall gain of approximately 65dB, with a bandpass-fil-

ter-type response centered near the 10.7MHz IF fre-

quency with a 3dB bandwidth of approximately 10MHz.

The RSSI circuit demodulates the IF by producing a DC

output proportional to the log of the IF signal level, with

a slope of approximately 14.2mV/dB (see the

Typical

Operating Characteristics

Applications Information

Crystal Oscillator

The crystal oscillator in the MAX7033 is designed to

present a capacitance of approximately 3pF between

the XTAL1 and XTAL2. If a crystal designed to oscillate

with a different load capacitance is used, the crystal is

pulled away from its stated operating frequency, intro-

ducing an error in the reference frequency. Crystals

designed to operate with higher differential load capac-

itance always pull the reference frequency higher. For

example, a 4.7547MHz crystal designed to operate

with a 10pF load capacitance oscillates at 4.7563MHz

with the MAX7033, causing the receiver to be tuned to

315.1MHz rather than 315.0MHz, an error of about

100kHz, or 320ppm.

In actuality, the oscillator pulls every crystal. The crys-

tal’s natural frequency is really below its specified fre-

quency, but when loaded with the specified load

capacitance, the crystal is pulled and oscillates at its

specified frequency. This pulling is already accounted

for in the specification of the load capacitance.

Additional pulling can be calculated if the electrical

parameters of the crystal are known. The frequency

pulling is given by:

where:

is the amount the crystal frequency pulled in ppm.

is the motional capacitance of the crystal.

CASE

is the case capacitance.

SPEC

is the specified load capacitance.

LOAD

is the actual load capacitance.

When the crystal is loaded as specified, i.e., C

LOAD

SPEC

, the frequency pulling equals zero.

It is possible to use an external reference oscillator in

place of a crystal to drive the VCO. AC-couple the exter-

nal oscillator to XTAL2 with a 1000pF capacitor. Drive

XTAL2 with a signal level of approximately -10dBm. AC-

couple XTAL1 to ground with a 1000pF capacitor.

Data Filter

The data filter is implemented as a 2nd-order lowpass

Sallen-Key filter. The pole locations are set by the com-

bination of two on-chip resistors and two external

capacitors. Adjusting the value of the external capaci-

tors changes the corner frequency to optimize for dif-

ferent data rates. The corner frequency should be set

to approximately 1.5 times the fastest expected data

rate from the transmitter. Keeping the corner frequency

near the data rate rejects any noise at higher frequen-

cies, resulting in an increase in receiver sensitivity.

The configuration shown in Figure 2 can create a

Butterworth or Bessel response. The Butterworth filter

offers a very flat amplitude response in the passband

and a rolloff rate of 40dB/decade for the two-pole filter.

The Bessel filter has a linear phase response, which

works well for filtering digital data. To calculate the

value of C5 and C6, use the following equations, along

with the coefficients in Table 2:

where f

is the desired 3dB corner frequency.

akf

100

4 100

()()()

CCCC

CASE LOAD CASE SPEC

⎛

⎝

⎜

⎞

⎠

⎟

MAX7033

315MHz/433MHz ASK Superheterodyne

Receiver with AGC Lock

12 ______________________________________________________________________________________

RSSI

DF1

100kΩ

DF2

100kΩ

DFO

OPP

DFFB

MAX7033

FILTER TYPE a b

Butterworth (Q = 0.707) 1.414 1.000

Bessel (Q = 0.577) 1.3617 0.618

Figure 2. Sallen-Key Lowpass Data Filter

Table 2. Coefficents to Calculate C5 and C6

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX7033ETJ+

Mfr. #:

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Manufacturer:

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Description:

RF Receiver 315MHz/433MHz ASK Superheterodyne Rec

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MAX7033ETJ+

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