SI4703-B17-GM Datasheet SI4703-B17-GMR, SI4703-B17-GM | P13-P15

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4. Functional Description

Figure 7. Si4703 FM Receiver Block Diagram

4.1. Overview

The Si4703 extends Silicon Laboratories Si4700 FM

tuner family, and further increases the ease and

attractiveness of adding FM radio reception to mobile

devices through small size and board area, minimum

component count, flexible programmability, and

superior, proven performance. Si4703 software is

backwards compatible to existing Si4701 FM Tuner

designs and leverages Silicon Laboratories' highly

successful and patented Si4701 FM tuner. The Si4703

benefits from proven digital integration and 100%

CMOS process technology, resulting in a completely

integrated solution. It is the industry's smallest footprint

FM tuner IC requiring only 10 mm

board space and

one external bypass capacitor.

The device offers significant programmability, and

caters to the subjective nature of FM listeners and

variable FM broadcast environments world-wide

through a simplified programming interface and mature

functionality.

The Si4703 incorporates a digital processor for the

European Radio Data System (RDS) and the US Radio

Broadcast Data System (RBDS) including all required

symbol decoding, block synchronization, error

detection, and error correction functions.

RDS enables data such as station identification and

song name to be displayed to the user. The Si4703

offers a detailed RDS view and a standard view,

allowing adopters to selectively choose granularity of

RDS status, data, and block errors. Si4703 software is

backwards compatible to the proven Si4701, adopted

by leading cell-phone and MP3 manufacturers

world-wide.

The Si4703 is based on the superior, proven

performance of Silicon Laboratories' Aero architecture

offering unmatched interference rejection and leading

sensitivity. The device uses the same programming

interface as the Si4701 and supports multiple

bus-modes. Power management is also simplified with

an integrated regulator allowing direct connection to a

2.7 to 5.5 V battery.

The Si4703 device’s high level of integration and

complete FM system production testing increases

quality to manufacturers, improves device yields, and

simplifies device manufacturing and final testing.

4.2. FM Receiver

The Si4703’s patented digital low-IF architecture

reduces external components and eliminates the need

for factory adjustments. The receive (RX) section

integrates a low noise amplifier (LNA) supporting the

worldwide FM broadcast band (76 to 108 MHz). An

automatic gain control (AGC) circuit controls the gain of

the LNA to optimize sensitivity and rejection of strong

interferers. For testing purposes, the AGC can be

disabled with the AGCD bit. Refer to Section 6.

"Register Descriptions" on page 20 for additional

programming and configuration information.

The Si4703 architecture and antenna design increases

VIO

CONTROLLER

ADC

Si4703

DSP

FILTER

DEMOD

MPX

AUDIO

SCLK

SDIO

CONTROL

INTERFACE

SEN

DAC

ROUT

LOUT

0 / 90 LOW-IF

RSSI

TUNE

GPIO

AMPLIFIER

GPIO

RST

RFGND

LNA

FMIP

AFC

AGC

PGA

RCLK

REG

32.768 kHz

2.7 - 5.5 V

Headphone

Cable

RDS

XTAL

OSC

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system performance. To ensure proper performance

and operation, designers should refer to the guidelines

in "AN231: Si4700/01/02/03 Headphone and Antenna

Interface". Conformance to these guidelines will help to

ensure excellent performance even in weak signal or

noisy environments.

An image-reject mixer downconverts the RF signal to

low-IF. The quadrature mixer output is amplified,

filtered, and digitized with high resolution

analog-to-digital converters (ADCs). This advanced

architecture achieves superior performance by using

digital signal processing (DSP) to perform channel

selection, FM demodulation, and stereo audio

processing compared to traditional analog

architectures.

4.3. General Purpose I/O Pins

The pins GPIO1–3 can serve multiple functions. GPIO1

and GPIO3 can be used to select between 2-wire and

3-wire modes for the control interface as the device is

brought out of reset. See Section “4.9. Reset, Powerup,

and Powerdown”. After powerup of the device, the

GPIO1–3 pins can be used as general purpose inputs/

outputs, and the GPIO2–3 pins can be used as interrupt

request pins for the seek/tune or RDS ready functions

and as a stereo/mono indicator respectively. See

Descriptions” for information on the control of these

pins. It is recommended that the GPIO2–3 pins not be

used as interrupt request outputs until the powerup time

has completed (see Section “4.9. Reset, Powerup, and

Powerdown”). The GPIO3 pin has an internal, 1 M,

±15% pull-down resistor that is only active while RST

low. General purpose input/output functionality is

available regardless of the state of the V

and V

supplies, or the ENABLE and DISABLE bits.

4.4. RDS/RBDS Processor and

Functionality

The Si4703 implements an RDS/RBDS* processor for

symbol decoding, block synchronization, error

detection, and error correction. RDS functionality is

enabled by setting the RDS bit. The device offers two

RDS modes, a standard mode and a verbose mode.

The primary difference is increased visibility to RDS

block-error levels and synchronization status with

verbose mode.

Setting the RDS mode (RDSM) bit low places the

device in standard RDS mode (default). The device will

set the RDS ready (RDSR) bit for a minimum of 40 ms

when a valid RDS group has been received. Setting the

RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 10

will configure GPIO2 to pulse low for a minimum of 5 ms

when a valid RDS group has been received. If an invalid

group is received, RDSR will not be set and GPIO2 will

not pulse low. In standard mode RDS synchronization

(RDSS) and block error rate A, B, C and D (BLERA,

BLERB, BLERC, and BLERD) are unused and will read

0. This mode is backward compatible with earlier

firmware revisions.

Setting the RDS mode bit high places the device in RDS

verbose mode. The device sets RDSS high when

synchronized and low when synchronization is lost. If

the device is synchronized, RDS ready (RDSR) will be

set for a minimum of 40 ms when a RDS group has

been received. Setting the RDS interrupt enable

(RDSIEN) bit and GPIO2[1:0] = 10 will configure GPIO2

to pulse low for a minimum of 5 ms if the device is

synchronized and an RDS group has been received.

BLERA, BLERB, BLERC and BLERD provide

block-error levels for the RDS group. The number of bit

errors in each block within the group is encoded as

follows: 00 = no errors, 01 = one to two errors, 10 =

three to five errors, 11 = six or more errors. Six or more

errors in a block indicate the block is uncorrectable and

should not be used.

The Si4703 offers an RDS high-performance mode for

RDS-only applications such as TMC (traffic message

channel) coupled with a GPS device. The RDS

performance bit RDSPRF 06h[9] is disabled by default

for backwards compatibility with previous RDS firmware

releases. When RDSPRF is enabled the device

increases power to the LNA, sets RDS to

unconditionally remain enabled, and disables FM

impulse detection, thereby avoiding RDS shutdown and

allowing the device to continue to track and decode

RDS in very poor SNR environments.

The Si4703-B17 device possesses an enhanced RDS/

TMC algorithm to improve RDS/TMC reception.

*Note: RDS/RBDS is referred to only as RDS throughout the

remainder of this document.

4.5. Stereo Audio Processing

The output of the FM demodulator is a stereo

multiplexed (MPX) signal. The MPX standard was

developed in 1961 and is used worldwide. Today's MPX

signal format consists of left + right (L+R) audio, left –

right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS

data as shown in Figure 8.

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Figure 8. MPX Signal Spectrum

The Si4703's integrated stereo decoder automatically

decodes the MPX signal. The 0 to 15 kHz (L+R) signal

is the mono output of the FM tuner. Stereo is generated

from the (L+R), (L-R), and a 19 kHz pilot tone. The pilot

tone is used as a reference to recover the (L-R) signal.

Separate left and right channels are obtained by adding

and subtracting the (L+R) and (L-R) signals,

respectively. The Si4703 uses frequency information

from the 19 kHz stereo pilot to recover the 57 kHz RDS/

RBDS signal.

Adaptive noise suppression is employed to gradually

combine the stereo left and right audio channels to a

mono (L+R) audio signal as the signal quality degrades

to maintain optimum sound fidelity under varying

reception conditions. The signal level range over which

the stereo to mono blending occurs can be adjusted by

setting the BLNDADJ[1:0] register. Stereo/mono status

can be monitored with the ST register bit and mono

operation can be forced with the MONO register bit.

Pre-emphasis and de-emphasis is a technique used by

FM broadcasters to improve the signal-to-noise ratio of

FM receivers by reducing the effects of high frequency

interference and noise. When the FM signal is

transmitted, a pre-emphasis filter is applied to

accentuate the high audio frequencies. All FM receivers

incorporate a de-emphasis filter which attenuates high

frequencies to restore a flat frequency response. Two

time constants, 50 or 75 µs, are used in various regions.

The de-emphasis time constant is programmable with

the DE bit.

High-fidelity stereo digital-to-analog converters (DACs)

drive analog audio signals onto the LOUT and ROUT

pins. The audio output may be muted with the DMUTE

bit. Volume can be adjusted digitally with the

VOLUME[3:0] bits. The volume dynamic range can be

set to either –28 dBFS (default) or –58 dBFS by setting

VOLEXT=1.

The soft mute feature is available to attenuate the audio

outputs and minimize audible noise in weak signal

conditions. The soft mute attack and decay rate can be

adjusted with the SMUTER[1:0] bits where 00 is the

fastest setting. The soft mute attenuation level can be

adjusted with the SMUTEA[1:0] bits where 00 is the

most attenuated. The soft mute disable (DSMUTE) bit

may be set high to disable this feature.

4.6. Tuning

The Si4703 uses Silicon Laboratories’ patented and

proven frequency synthesizer technology including a

completely integrated VCO. The frequency synthesizer

generates the quadrature local oscillator signal used to

downconvert the RF input to a low intermediate

frequency. The VCO frequency is locked to the

reference clock and adjusted with an automatic

frequency control (AFC) servo loop during reception.

The tuning frequency is defined as:

Channel spacing of 50, 100 or 200 kHz is selected with

bits SPACE[1:0]. The channel is selected with bits

CHAN[9:0]. Band selection for Japan, Japan wideband,

or Europe/U.S./Asia is set with BAND[1:0]. The tuning

operation begins by setting the TUNE bit. After tuning

completes, the seek/tune complete (STC) bit will be set

and the RSSI level is available by reading bits

RSSI[7:0]. The TUNE bit must be set low after the STC

bit is set high in order to complete the tune operation

and clear the STC bit.

Seek tuning searches up or down for a channel with an

RSSI greater than or equal to the seek threshold set

with the SEEKTH[7:0] bits. In addition, optional SNR

and/or impulse noise detector criteria may be used to

qualify valid stations. The SKSNR[3:0] bits set the SNR

threshold required. The SKCNT[3:0] bits set the impulse

noise threshold. Using the extra seek qualifiers can

reduce false stops and, in combination with lowering the

RSSI seek threshold, increase the number of found

stations. The SNR and impulse noise detectors are

disabled by default for backwards compatibility.

Two seek modes are available. When the seek mode

(SKMODE) bit is low and a seek is initiated, the device

seeks through the band, wraps from one band edge to

the other, and continues seeking. If the seek operation

is unable to find a valid channel, the seek failure/band

limit (SF/BL) bit is set high and the device returns to the

channel selected before the seek operation began.

When the SKMODE bit is high and a seek is initiated,

the device seeks through the band until the band limit is

reached and the SF/BL bit is set high. A seek operation

is initiated by setting the SEEK and SEEKUP bits. After

the seek operation completes, the STC bit is set, and

the RSSI level and tuned channel are available by

reading bits RSSI[7:0] and bits READCHAN[9:0]. During

a seek operation READCHAN[9:0] is also updated and

may be read to determine and report seek progress.

0575338231915

Frequency (kHz)

Modulation Level

Stereo Audio

Left - Right

RDS/

RBDS

Mono Audio

Left + Right

Stereo

Pilot

Freq (MHz) Spacing (kHz) Channel Bottom of Band (MHz)+=

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

SI4703-B17-GM

Mfr. #:

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Manufacturer:

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Description:

Tuners FM receiver with RDS

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SI4703-B17-GM

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