OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SI4703-B17-GM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
Si4703-B17
16 Confidential Rev. 1.0
N
ot R
ecom
m
ende
d for N
ew D
esi
gns
The STC bit is set after the seek operation completes.
The channel is valid if the seek operation completes and
the SF/BL bit is set low. At other times, such as before a
seek operation or after a seek completes and the SF/BL
bit is set high, the channel is valid if the AFC Rail
(AFCRL) bit is set low and the value of RSSI[7:0] is
greater than or equal to SEEKTH[7:0]. Note that if a
valid channel is found but the AFCRL bit is set, the
audio output is muted as in the softmute case discussed
in Section “4.5. Stereo Audio Processing”. The SEEK bit
must be set low after the STC bit is set high in order to
complete the seek operation. Setting the STC bit high
clears STC status and SF/BL bits. The seek operation
may be aborted by setting the SEEK bit low at any time.
The device can be configured to generate an interrupt
on GPIO2 when a tune or seek operation completes.
Setting the seek/tune complete (STCIEN) bit and
GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low
interrupt when the STC bit is set by the device.
For additional recommendations on optimizing the seek
function, consult "AN284: Si4700/01/02/03 Seek
Adjustability and Settings."
4.7. Reference Clock
The Si4703 accepts a 32.768 kHz reference clock to the
RCLK pin. The reference clock is required whenever the
ENABLE bit is set high. Refer to Table 3, “DC
Characteristics,” on page 5 for switching voltage levels
and Table 7, "FM Receiver Characteristics," on page 10
for frequency tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to 2. "Typical Application
Schematic" on page 12. The oscillator must be enabled
or disabled while in powerdown (ENABLE = 0) as shown
in Figure 9, “Initialization Sequence,” on page 18.
Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown.
4.7.1. Si4703 Internal Crystal Oscillator Errata
The Si4703-B17 seek/tune performance may be
affected by data activity on the SDIO bus when using
the integrated internal oscillator. SDIO activity results
from polling the tuner for status or communicating with
other devices that share the SDIO bus. If there is SDIO
bus activity while the Si4703-B17 is performing the
seek/tune function, the crystal oscillator may experience
jitter, which may result in mistunes and/or false stops.
SDIO activity during all other operational states does
not affect performance.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4703-B17 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
Please refer to the Si4703-B17 data sheet for specified
seek/tune times and register use guidelines.
The layout guidelines in Si4700/01/02/03 Evaluation
Board User’s Guide, Section 8.3 Si4703 Daughter Card
should be followed to help ensure robust FM
performance.
Please refer to the posted Si4702/03 Internal Crystal
Oscillator Errata for more information.
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V
IO
supply
is applied regardless of the state of the V
D
or V
A
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
For three-wire operation, a transfer begins when the
SEN
pin is set low on a rising SCLK edge. The control
word is latched internally on rising SCLK edges and is
nine bits in length, comprised of a four bit chip address
A7:A4 = 0110b, a read/write bit (write = 0 and read = 1),
and a four bit register address, A3:A0. The ordering of
the control word is A7:A5, R/W
, A4:A0. Refer to Section
5. "Register Summary" on page 19 for a list of all
registers and their addresses.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN
is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 7, Figure 3, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 4, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
Si4703-B17
Confidential Rev. 1.0 17
N
ot Recommend
e
d for New
D
esigns
4.8.2. 2-wire Control Interface
For two-wire operation, a transfer begins with the
START condition. The control word is latched internally
on rising SCLK edges and is eight bits in length,
comprised of a seven bit device address equal to
0010000b and a read/write bit (write = 0 and read = 1).
The device acknowledges the address by setting SDIO
low on the next falling SCLK edge.
For write operations, the device acknowledge is
followed by an eight bit data word latched internally on
rising edges of SCLK. The device always acknowledges
the data by setting SDIO low on the next falling SCLK
edge. An internal address counter automatically
increments to allow continuous data byte writes, starting
with the upper byte of register 02h, followed by the
lower byte of register 02h, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous writes cease. Data transfer ceases with the
STOP command. After every STOP command, the
internal address counter is reset.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC should return an acknowledge if an
additional byte of data will be requested. Data transfer
ceases with the STOP command. After every STOP
command, the internal address counter is reset.
For details on timing specifications and diagrams, refer
to Table 6, “2-Wire Control Interface Characteristics
1
,”
on page 8, Figure 5, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 9 and Figure 6,
“2-Wire Control Interface Read and Write Timing
Diagram,” on page 9.
4.9. Reset, Powerup, and Powerdown
Driving the RST pin low will disable the Si4703 and its
control bus interface, and reset the registers to their
default settings. Driving the RST
pin high will bring the
device out of reset. As the part is brought out of reset,
one of two methods may be used to select between
2-wire and 3-wire control interface operation.
Busmode select method 1 requires the use of the
GPIO3, SEN
, and SDIO pins. The GPIO3 pin should be
externally driven low, set to hi-Z or left floating, and the
SDIO pin should be externally driven low on the rising
edge of RST
. The GPIO3 pin has an internal 1 M
pulldown resistor to ensure proper bus mode selection.
To select 2-wire operation of the control interface, the
SEN
pin should be externally driven high on the rising
edge of RST
. To select 3-wire operation of the control
interface, the SEN
pin should be externally driven low
on the rising edge of RST
. Refer to Table 4, “Reset
Timing Characteristics,” on page 6 and Figure 1, “Reset
Timing Parameters for Busmode Select Method 1,” on
page 6.
Busmode select method 2 only requires the use of the
GPIO3 and GPIO1 pins. The GPIO3 pin should be
driven high on the rising edge of RST
. Using this control
interface bus selection method, a 100 k or lower
pull-up resistor should be used on the GPIO3 pin. To
select 2-wire operation of the control interface, the
GPIO1 and GPIO3 pins should be externally driven high
on the rising edge of RST
. To select 3-wire operation of
the control interface, the GPIO1 pin should be externally
driven low on the rising edge of RST
. Refer to Table 4,
“Reset Timing Characteristics,” on page 6 and Figure 2,
“Reset Timing Parameters for Busmode Select Method
2,” on page 6. Table 8 below summarizes the two bus
selection methods.
Table 8. Selecting 2-Wire or 3-Wire Control
Interface Busmode Operation
1
Busmode
Select Method
SEN SDIO GPIO1
GPIO3
2
Bus
mode
1 0 0 X 0
3
3-wire
1 1 0 X 0
3
2-wire
1
Xtal Oscillator
0 0 X 0
4
3-wire
1
Xtal Oscillator
1 0 X 0
4
2-wire
2 X X 0 1
5
3-wire
2 X X 1 1
5
2-wire
2
Xtal Oscillator
NA NA NA NA NA
2
Xtal Oscillator
NA NA NA NA NA
Notes:
1. All parameters applied on rising edge of RST
.
2. GPIO3 is internally pulled down with a 1 M resistor.
3. GPIO3 should be externally driven low, set to high-Z
(10 M or greater pull-up) or float.
4. GPIO3 should be left floating.
5. GPIO3 should be externally driven high (100 kor
smaller pull-up).
Si4703-B17
18 Confidential Rev. 1.0
N
ot R
ecom
m
ende
d for N
ew D
esi
gns
When proper voltages are applied to the Si4703, the
ENABLE and DISABLE bits in register 02h can be used
to select between powerup and powerdown modes.
When voltage is first applied to the device, ENABLE = 0
and DISABLE = 0. Setting ENABLE = 1 and DISABLE
= 0 puts the device in powerup mode. To power down
the device, the ENABLE and DISABLE bits should both
be written to 1. After being written to 1, both bits will be
cleared as part of the internal device powerdown
sequence. To put the device back into powerup mode,
set ENABLE = 1 and DISABLE = 0 as described above.
The ENABLE bit should never be written to a 0.
4.10. Audio Output Summation
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x V
IO
on the LOUT and ROUT pins to prevent the
ESD diodes from clamping to the V
IO
or GND rail in
response to the output swing of the other device. The
bias point is set with a 370 k resistor to V
IO
and GND.
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and V
IO
is supplied. In
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 7, “FM
Receiver Characteristics
1,2
,” on page 10, regardless of
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
4.11. Initialization Sequence
Refer to Figure 9, “Initialization Sequence,” on page 18.
To initialize the device:
1. Supply V
A
and V
D
.
2. Supply V
IO
while keeping the RST pin low. Note that steps
1 and 2 may be reversed. Power supplies may be
sequenced in any order.
3. Select 2-wire or 3-wire control interface bus mode
operation as described in Section 4.9. "Reset, Powerup,
and Powerdown" on page 17.
4. Provide RCLK. Steps 3 and 4 may be reversed when using
an external oscillator. Wait 500 ms for oscillator startup
when using internal oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device. Software should wait for the powerup
time (as specified by Table 7, “FM Receiver
Characteristics
1,2
,” on page 10) before continuing with
normal part operation.
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc bias of
0.5 x V
IO
volts at the LOUT and ROUT pins while in
powerdown, but preserve the states of the other bits in
Register 07h. Note that in powerup the LOUT and ROUT
pins are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of AHIZEN.
2. Set the ENABLE bit high and the DISABLE bit high to
place the device in powerdown mode. Note that all register
states are maintained so long as V
IO
is supplied and the
RST
pin is high.
3. (Optional) Remove RCLK.
4. Remove V
A
and V
D
supplies as needed.
To power up the device (after power down):
1. Note that V
IO
is still supplied in this scenario. If V
IO
is not
supplied, refer to device initialization procedure above.
2. (Optional) Set the AHIZEN bit low to disable the dc bias of
0.5 x V
IO
volts at the LOUT and ROUT pins, but preserve
the states of the other bits in Register 07h. Note that in
powerup the LOUT and ROUT pins are set to the common
mode voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
3. Supply V
A
and V
D
.
4. Provide RCLK. Wait 500 ms for oscillator startup when
using internal oscillator.
5. Set the ENABLE bit high and the DISABLE bit low to
powerup the device.
Figure 9. Initialization Sequence
4.12. Programming Guide
Refer to "AN230: Si4700/01 Programming Guide" for
control interface programming information.
VA,VD Supply
RCLK Pin
ENABLE Bit
1234
5
RST Pin
VIO Supply
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

SI4703-B17-GM

Mfr. #:
Buy SI4703-B17-GM
Manufacturer:
Silicon Labs
Description:
Tuners FM receiver with RDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet