Si4703-B17
8 Confidential Rev. 1.0
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Table 6. 2-Wire Control Interface Characteristics
1
(V
D
= V
A
= 2.7 to 5.5 V, V
IO
= 1.5 to 3.6 V, T
A
= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
SCLK Frequency f
SCL
0—400kHz
SCLK Low Time t
LOW
1.3 — — µs
SCLK High Time t
HIGH
0.6 — — µs
SCLK Input to SDIO
Setup
(START)
t
SU:STA
0.6 — — µs
SCLK Input to SDIO
Hold (START) t
HD:STA
0.6 — — µs
SDIO Input to SCLK
Setup t
SU:DAT
100 — — ns
SDIO Input to SCLK
Hold
2,3
t
HD:DAT
0—900ns
SCLK input to SDIO
Setup (STOP) t
SU:STO
0.6 — — µs
STOP to START Time t
BUF
1.3 — — µs
SDIO Output Fall Time t
f:OUT
20 + 01.C
b
—250ns
SDIO Input, SCLK Rise/Fall Time t
f:IN
t
r:IN
20 + 01.C
b
—300ns
SCLK, SDIO Capacitive Loading C
b
——50pF
Input Filter Pulse Suppression t
SP
— — 50 ns
Notes:
1. When V
IO
= 0 V, SCLK and SDIO are low impedance.
2. As a transmitter, the Si4703 delays SDIO by a minimum of 300 ns from the V
IH
threshold of SCLK to comply with the
0 ns t
HD:DAT
specification.
3. The maximum t
HD:DAT
has only to be met when f
SCL
= 400 kHz. At frequencies below 400 KHz, t
HD:DAT
may be
violated so long as all other timing parameters are met.
