IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
3
Datasheet
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 VDD PWR Power supply, nominal 3.3V
2OE10# IN
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
3 DIF_10 OUT 0.7V differential true clock output
4 DIF_10# OUT 0.7V differential complement clock output
5OE11# IN
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
6 DIF_11 OUT 0.7V differential true clock output
7 DIF_11# OUT 0.7V differential complement clock output
8OE12# IN
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
9 DIF_12 OUT 0.7V differential true clock output
10 DIF_12# OUT 0.7V differential complement clock output
11 GND PWR Ground pin.
12 VDD PWR Power supply, nominal 3.3V
13 DIF_13 OUT 0.7V differential true clock output
14 DIF_13# OUT 0.7V differential complement clock output
15 OE13# IN
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
16 DIF_14 OUT 0.7V differential true clock output
17 DIF_14# OUT 0.7V differential complement clock output
18 OE14# IN
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
19 DIF_15 OUT 0.7V differential true clock output
20 DIF_15# OUT 0.7V differential complement clock output
21 VDD PWR Power supply, nominal 3.3V
22 OE15_17# IN
Active low input for enabling DIF pairs 15, 16 and 17
1 = tri-state outputs, 0 = enable outputs
23 DIF_16 OUT 0.7V differential true clock output
24 DIF_16# OUT 0.7V differential complement clock output
25 DIF_17 OUT 0.7V differential true clock output
26 DIF_17# OUT 0.7V differential complement clock output
27 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475
ohms is the standard value.
28 GNDA PWR Ground pin for the PLL core.
29 VDDA PWR 3.3V power for the PLL core.
30 CLKA_IN IN True Input for differential reference clock.
31 CLKA_IN# IN Complement Input for differential reference clock.
32 GND PWR Ground pin.
33 CLKB_IN IN True Input for differential reference clock.
34 CLKB_IN# IN Complement Input for differential reference clock.
35 VDD PWR Power supply, nominal 3.3V
36 OE_01234# IN
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
