IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
7
Datasheet
Electrical Characte ristics - Skew and Differential Jitter Parameters
T
A
= T
COM
or T
IND
; Supply Voltage V
DD
= 3 .3 V +/-5%
Group Parameter Description Min TYP Max Units Notes
CLK_IN, DIF[x:0]
t
SPO_PLL100M
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25°C
,
3.3V
,
100MHz
950 1000 1125 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
SPO_PLL133M
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25 °C, 3.3V, 133MHz
1100 1125 1175 ps 1,2,4,5,8
CLK_IN, DIF[x:0]
t
PD_BYP
Input-to-Output Skew in Bypass mode (1:1 only),
nominal value @ 25°C, 3.3V
4 4.7 5.2 ns 1,2,3,5
CL K _ IN , D IF [x :0 ]
8
t
SP O_ PLL
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating ranges)
|250| |350| ps
1,2,4,5,6,
10
CL K _ IN , D IF [x :0 ]
8
t
PD_ BY P
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
|800| |900| ps
1,2,3,4,5,
6,10
DIF[17:0] t
SKEW_A19
Output-to-Output Skew across all 18 outputs
(Common to Bypass and PLL mode - all outputs at same gear)
100 150 ps 1,2,3
DIF[17:0] t
JPH
Differential Phase Jitter (RMS Value) 2 10 ps 1,4,7
DIF[17:0]
t
SSTERROR
Differential Spread Spectrum Tracking Error (peak to peak) 20 80 ps 1,4,9
NOTES:
8. t is the period of the input clock
10. This parameter is an absolute value. It is not a double-sided figure.
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two ICS9EX21801 devices This parameter is measured at the outputs of
two separate ICS9EX21801 devices driven by a single CK410B+ in Spread Spectrum mode. The ICS9EX21801's must be set to high ba ndwidth. The spread spectrum
characteristics are: maximum of 0.5%, 30-33KHz modulation frequency, linear profile.
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate ICS9EX21801 devices driven by a single CK410B+. The ICS9EX21801's must be set to high bandwidth.
Differential phase jitter is the accumulation of the phase jitte r not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are
a
g
ents with BW of 1-22Mhz and 11-33Mhz.
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the fi rst output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
8
Datasheet
Electrical Characteristics - Phase Jitter
(
PLL Mode
)
PARAMETER SYMBOL CONDITIONS* MIN TYP. MAX UNITS
NOTES
PLL Bandwidth BWH High Bandwidth Selected 2 3 4 MHz
PLL Bandwidth BWL Low Bandwidth Selected 0.7 1 2 MHz
PLL Jitter Peaking jPKH High Bandwidth Selected 2.5 3 dB
PLL Jitter Peaking jPKL Low Ba ndwidth Selected 2 2.5 dB
PCIe Gen 1
(
1.5 - 22 MHz
)
36/42 108 ps 1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Lo-band content
(
10kHz to 1.5MHz
)
1.1/1.2 3 ps rms 1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Hi-band content
(
1.5M Hz to N
yq
uist
)
2.0/2.1 3.1 ps rms 1, 2
QPI_133MHz (4.8Gb, 12 UI) 0.24/0.25 0.5 ps rms 2, 3
QPI_133MHz (6.4Gb, 12 UI) 0.18/0.19 0.5 ps rms 2, 3
PCIe Gen 1
(1 .5 - 22 MHz)
28/32 86 ps 1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Lo-band content
(
10kHz to 1.5MHz
)
1.2/1.5 3 ps rms 1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Hi-band content
(
1.5M Hz to N
yq
uist
)
2.6/2.7 3.1 ps rms 1,2
QPI_133MHz (4.8Gb, 12 UI) 0.27/0.28 0.5 ps rms 2, 3
QPI_133MHz (6.4Gb, 12 UI) 0.2/0.21 0.5 ps rms 2, 3
Notes on Phase Jitter: (Guaranteed by design and characterization, not tested in production)
1
See http://www.pcisig.com for complete specs. First number is Spread Spectrum Off, second is Spread Spectrum On.
2
Device driven by IDT CK410B+ (932S421CGLF) or CK509B (932S509EKLF) or equivalent
3
Calculated from Intel Su
pp
lied Clock Jitter Tool 1.5.1. First number is S
p
read S
p
ectrum Off, second is S
p
read S
p
ectrum On
Jitter, Phase
tjphase_LoBW
tjphase_H IBW
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
9
Datasheet
General SMBus serial interface information for the 9EX21801A
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D4
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address D4
(h)
*
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D5
(h)
*
Index Block Read Operation
Slave Address D4
(h)
*
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Note: The address is selectable among 4 values (page 2).

9EX21801AKILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIE BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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