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9EX21801AKILFT

P1-P3P4-P6P7-P9P10-P12P13-P14
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
4
Datasheet
Pin Description (continued)
PIN # PIN NAME PIN TYPE DESCRIPTION
37 DIF_0 OUT 0.7V differential true clock output
38 DIF_0# OUT 0.7V differential complement clock output
39 DIF_1 OUT 0.7V differential true clock output
40 DIF_1# OUT 0.7V differential complement clock output
41 DIF_2 OUT 0.7V differential true clock output
42 DIF_2# OUT 0.7V differential complement clock output
43 VDD PWR Power supply, nominal 3.3V
44 GND PWR Ground pin.
45 DIF_3 OUT 0.7V differential true clock output
46 DIF_3# OUT 0.7V differential complement clock output
47 DIF_4 OUT 0.7V differential true clock output
48 DIF_4# OUT 0.7V differential complement clock output
49 OE5# IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
50 DIF_5 OUT 0.7V differential true clock output
51 DIF_5# OUT 0.7V differential complement clock output
52 OE6# IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
53 DIF_6 OUT 0.7V differential true clock output
54 DIF_6# OUT 0.7V differential complement clock output
55 VDD PWR Power supply, nominal 3.3V
56 OE7# IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
57 DIF_7 OUT 0.7V differential true clock output
58 DIF_7# OUT 0.7V differential complement clock output
59 OE8# IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
60 DIF_8 OUT 0.7V differential true clock output
61 DIF_8# OUT 0.7V differential complement clock output
62 100M_133M# IN
Input to select operating frequency. See Frequency/Functionality Table for functionality of this
pin.
63 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass Mode or Low BW.
0 = Low BW Mode, Mid= Bypass Mode, 1 = Hi
g
h Bandwidth
64 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
65 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
66 SMB_A1 IN SMBus address bit 1
67 SMB_A0 IN SMBus address bit 0 (LSB)
68 SEL_A_B# IN
Input to select differential input clock A or differential input clock B.
0 = Input B selected, 1 = Input A selected.
69 CKPWRGD/PD# IN
Notifies the clock to sample latched inputs on the rising edge, and to power down on the falling
ed
g
e.
70 DIF_9 OUT 0.7V differential true clock output
71 DIF_9# OUT 0.7V differential complement clock output
72 OE9# IN
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
5
Datasheet
Absolute Maximum Ratings
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage VDDA Analog PLL Supply, referenced to GND -0.5 4.6 V
1
3.3V Logic Supply
Voltage VDD Main power supply , referenced to GND -0.5 4.6 V
1
Storage Temperature Ts -65 150
°
C1
T
COM
070°C
1
T
IND
-4 0 85 °C 1
C ase Tempe rature Tcase 115 °C 1
Input ESD protection ESD prot Human Body Model 2000 V 1
Ambient Operating Temp
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= T
COM
or T
IND
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage
V
IH
3.3 V +/-5%, referenced to GND 2 3.6 V
Input Low Voltage V
IL
3.3 V +/-5%, referen ced to GND -0.3 0.8 V
Input High Current
I
IH
V
IN
= V
DD
-5 5 uA
I
IL1
V
IN
= 0 V; Inputs w/o pull-up resistors -5 uA
I
IL2
V
IN
= 0 V; Inputs w/ pull-up resistors
-200 uA
Digital Supply Current
I
DD 3.3D
VDD, Full Active, C
L
= Full load;
450 mA 1
Analog Supply Current
I
DD3.3A
VDDA, Full Active, C
L
= Full load;
40 mA 1
Di
g
ital Powerdown
Current
I
DD 3.3DPD
all differential pairs tri-stated 15 mA 1
Analog Powerdown
Current
I
DD 3.3APD
all differential pairs tri-stated 20 mA 1
F
iPL L
100MHz PLL Mode 80 110 MHz 1
F
iPL L
133MHz PLL Mode 90 150 MHz 1
F
iBYPASS
Bypass Mode 33 400 MHz 1
Pin Inductance L
pin
7nH1
C
IN
Logic Inputs 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Clk Stab iliz ation
T
STAB
From V
DD
Power-Up and after input
clock stabilization or de-assertion of PD#
to 1st clock
1ms1
Allowable Spread
Modulation Fre
q
uenc
y
f
MOD
Triangular Modulation 30 33 kHz 1,3
OE# Latency
t
LAT OE#
DIF start after OE# assertion
DIF sto
p
after OE# deassertion
4 12 cycles 1,2
Tdrive_PD
t
DRVPD
DIF output enable after
PD de-assertion
300 us 1,2
Tf all t
F
Fall time of OE# 5 ns 1
Trise t
R
Rise time of OE# 5 ns
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro ductio n.
2
Time from deassertion until outputs are >200 mV
Capacitance
Input Low Current
3
For which spread spectrum tracking error spec will be met.
Input Frequency
IDT
®
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux 1463E — 07/20/11
9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
6
Datasheet
Electrical Characteristics - Clock Input Parameters
T
A
= T
COM
or T
IND
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage -
DIF_IN
V
IHD IF
Differential in puts
sin
le-ended measurement
600 800 1150 mV 1
Input Low Voltage -
DIF_IN
V
IL DIF
Differential in puts
sin
le-ended measurement
V
SS
- 300 0 3 00 mV 1
Input Common Mode
Volta
g
e - DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_ IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current
I
IN
V
IN
= V
D D ,
V
IN
=
GN D
-5 5 uA 1
Input Duty Cycle
d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to
Cycle
J
DIF In
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h Vswin
g
min centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Pairs
T
A
= T
COM
or T
IND
; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33 .2
Ω
, R
P
=49 .9
Ω
, R
REF
=4 75
Ω
, 10 inch transmission lines
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance
Zo
1
V
O
= V
x
3000
Ω
1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
eVovs 1150 1
Min Volta
g
eVuds -300 1
Crossing Voltage (abs) Vcross(abs) 250 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossin g over all edges 140 mV 1
Long Accuracy ppm see Tperiod min-max values 0 ppm 1,2
Rise Time t
r
V
OL
= 0.175V, V
OH
= 0.525V 175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 700 ps 1
Rise Time Variation d-t
r
125 ps 1
Fa ll Time Variation
d-t
f
125 ps 1
Duty Cycle
d
t3
Measurement from differential wavefrom 45 55 % 1
PLL mo de 50
p
s1,5
BYPASS mode as additive
j
itter 50
p
s1,4
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
ro ductio n.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1 %), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
4
A
pp
lies to B
yp
ass Mode Onl
y
5
Measured from differential waveform
mV
Statistical measurement on single ended
signal using oscilloscope math function.
mV
Measurement on single ended signal
using absolute value.
Jitter, Cycle to cycle
t
jcyc-cyc
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK410B+/CK509B accuracy requirements. The 9EX21801 itself does not contribu te to ppm error.
P1-P3P4-P6P7-P9P10-P12P13-P14

9EX21801AKILFT

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Buy 9EX21801AKILFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products PCIE BUFFER
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