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SY100EP196VTG-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
10
ECL Pro®
SY100EP196V
Micrel
M0644-012704
Invalid
Invalid
Invalid
V
CC
V
IH(MAX)
V
IH(MIN)
V
IL(MAX)
Logic High
V
IL(MIN)
0V
Logic Low
Figure 4a. Input Levels, PECL
Invalid
Invalid
Invalid
V
CC
V
IH(MIN)
V
IL(MAX)
Logic High
0V
Logic Low
Figure 4b. Input Levels, CMOS, TTL
Invalid
Invalid
Invalid
0V
V
IH(MAX)
V
IH(MIN)
V
IL(MAX)
Logic High
V
IL(MIN)
V
EE
Logic Low
Figure 4c. Input Levels, NECL
V
IHCMR
0V
IN
/IN
Figure 5a. Input Common Mode, PECL, LVPECL
V
IHCMR
V
IHCMR
0V
IN
/IN
Figure 5b. Input Common Mode, NECL
11
ECL Pro®
SY100EP196V
Micrel
M0644-012704
R2
82Ω
R2
82Ω
Z
O
= 50Ω
Z
O
= 50Ω
+3.3V
+3.3V
V
t
= V
CC
—2V
R1
130Ω
R1
130Ω
+3.3V
Figure 6a. Parallel Termination—Thevenin Equivalent
Note:
1. For +5.0V systems: R1 = 82Ω, R2 = 130Ω.
Z
= 50Ω
Z
= 50Ω
50Ω 50Ω
50Ω
+3.3V +3.3V
Source Destination
R
b
C1 (optional)
0.01µF
Figure 6b. Three-Resistor “Y-Termination”
Notes:
1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. R
b
resistor sets the DC bias voltage, equal to V
t
. For +3.3V systems R
b
= 46Ω to 50Ω. For +5V systems, R
b
= 110Ω.
+3.3V +3.3V
Z
O
= 50Ω
R2
82Ω
+3.3V +3.3V
R1
130Ω
R1
130Ω
R2
82Ω
V
t
= V
CC
—2V
Q
/Q
50Ω
+3.3V
0.01µF
V
BB
Figure 6c. Terminating Unused I/O
Notes:
1. Unused output (/Q) must be terminated to balance the output.
2. Micrel's differential I/O logic devices include a V
BB
reference pin .
3. Connect unused input through 50Ω to V
BB
. Bypass with a 0.01µF capacitor to V
CC
, not GND, as PECL is referenced to V
CC
.
TERMINATING PECL
12
ECL Pro®
SY100EP196V
Micrel
M0644-012704
PECL
Output
V
BB
V
CC
SY100EP196V
IN
0.01µF
/IN
Figure 7a. Interfacing to a
Single-Ended PECL Signal
PECL
Output
V
BB
V
CC
SY100EP196V
IN
0.01µF
/IN
Figure 7b. Interfacing to and Inverting
a Single-Ended PECL Signal
5050
V
BB
SY100EP196V
IN
/IN
V
CC
0.01µF
Figure 8. Re-Biasing an AC-Coupled Signal
V
EF
V
CF
SY100EP196V
D[0:10]
PECL
Signals
V
CC
+5.0V
V
EE
0V
Figure 9a. Connecting PECL Signals
to the D Inputs
V
EF
V
CF
SY100EP196V
D[0:10]
LVPECL
Signals
V
CC
+3.3V
V
EE
0V
Figure 9b. Connecting LVPECL Signals
to the D Inputs
V
EF
V
CF
NC
NC
SY100EP196V
D[0:10]
CMOS
Inputs
V
CC
+3.3V or +5.0V
V
EE
0V
Figure 9c. Connecting CMOS Signals
to the D Inputs
Note: V
CF
and V
EF
are not connected
V
EF
NC
V
CF
SY100EP196V
D[0:10]
TTL
Inputs
V
CC
+3.3V
V
EE
0V0V
1.5k
Figure 9d. Connecting TTL Signals
to the D Inputs with V
CC
= 3.3V
V
EF
NC
V
CF
SY100EP196V
D[0:10]
TTL
Inputs
V
CC
+5.0V
V
EE
0V0V
500
Figure 9e. Connecting TTL Signals
to the D Inputs with V
CC
= 5.0V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

SY100EP196VTG-TR

Mfr. #:
Buy SY100EP196VTG-TR
Manufacturer:
Microchip Technology / Micrel
Description:
Delay Lines / Timing Elements 3.3V/5V 2.5 GHz Programmable Delay Line w/Fine Tune
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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