7
ECL Pro®
SY100EP196V
Micrel
M0644-012704
AC ELECTRICAL CHARACTERISTICS
V
CC
= 3.0 to 5.5V, V
EE
= 0V or V
CC
= 0V, V
EE
= –3.0 to –5.5V; T
A
= –40°C to +85°C
(12, 13)
T
A
= –40°CT
A
= +25°CT
A
= +85°C
Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit
f
MAX
Maximum Frequency
(14)
2.5 2.5 2.5 GHz
t
PD
Propagation Delay
IN to Q; D[0-10]=0 1650 2000 2450 1800 2050 2600 1950 2250 2750 ps
IN to Q; D[0-10]=1023 9500 11500 13500 9800 12200 14000 10600 13300 15800 ps
/EN to Q: D[0-10]=0 1600 2150 2600 1800 2300 2800 2000 2500 3000 ps
D10 to CASCADE 300 420 500 325 450 550 325 525 625 ps
t
RANGE
Programmable Range
t
PD
(max)-t
PD
(min) 7850 9450 8200 10000 8850 10950 ps
∆t Step Delay
(15)
D0 High 9 10 10 ps
D1 High 25 26 27 ps
D2 High 42 42 43 ps
D3 High 75 80 81 ps
D4 High 142 143 150 ps
D5 High 296 300 310 ps
D6 High 532 540 565 ps
D7 High 1080 1095 1140 ps
D8 High 2100 2150 2250 ps
D9 High 4250 4300 4500 ps
Lin Linearity
(16)
±10 ±10 ±10 %LSB
t
SKEW
Duty Cycle Skew
(17)
t
PHL
-t
PLH
25 ps
t
S
Setup Time D to LEN 200 0 200 0 200 0 ps
D to IN
(18)
300 140 300 160 300 180 ps
/EN to IN
(19)
300 150 300 170 300 180 ps
t
H
Hold Time LEN to D 200 60 200 100 200 80 ps
IN to /EN
(20)
400 250 400 280 400 300 ps
t
R
Release Time
/EN to IN
(21)
500 ps
SETMAX to LEN 400 200 400 250 400 300 ps
SETMIN to LEN 350 275 350 200 350 335 ps
t
JIT
Cycle-to-Cycle Jitter
(22)
0.2 < 1 0.2 < 1 0.2 < 1 ps
rms
V
PP
Input Voltage Swing (Differential) 150 800 1200 150 800 1200 150 800 1200 mV
t
r
Output Rise/Fall Time
t
f
20% to 80% (Q) 180 250 210 300 230 325 ps
20% to 80% (CASCADE) 180 250 210 300 230 325 ps
Notes:
12. AC characteristics are guaranteed by design and characterization.
13. Measured using 750mV source, 50% duty cycle clock source.
14. Refer to
“Typical Operating Characteristics”
for output swing performance.
15. The delays of the individual bits are cumulative.
16. Linearity is the deviation from the ideal delay.
17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding
output edge.
18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge.
19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to that
IN, /IN transition.
20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to that IN, /IN transition.
21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency
between 0.0 and 2.5GHz.
