ATUC256L3U-Z3UT Datasheet ATUC256L3U-Z3UT, ATUC256L4U-AUT | P31-P33

32142DS–06/2013

ATUC64/128/256L3/4U

4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

NCPHA=0

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1

if CSRn.CPOL=1 and CSRn.NCPHA=0.

5. SPI mode fault detection enable causes incorrect behavior

When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate

properly.

Fix/Workaround

Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.

6. SPI RDR.PCS is not correct

The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not

correctly indicate the value on the NPCS pins at the end of a transfer.

Fix/Workaround

Do not use the PCS field of the SPI RDR.

6.1.3 TWI

1. SMBALERT bit may be set after reset

The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after

system reset.

Fix/Workaround

After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.

2. Clearing the NAK bit before the BTF bit is set locks up the TWI bus

When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-

ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to

attempt to continue transmitting data, thus locking up the bus.

Fix/Workaround

Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been

set.

6.1.4 TC

1. Channel chaining skips first pulse for upper channel

When chaining two channels using the Block Mode Register, the first pulse of the clock

between the channels is skipped.

Fix/Workaround

Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle

for the upper channel. After the dummy cycle has been generated, indicated by the

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real

values.

6.1.5 CAT

1. CAT QMatrix sense capacitors discharged prematurely

At the end of a QMatrix burst charging sequence that uses different burst count values for

different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-

32142DS–06/2013

ATUC64/128/256L3/4U

eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.

This results in premature loss of charge from the sense capacitors and thus increased vari-

ability of the acquired count values.

Fix/Workaround

Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,

13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.

2. Autonomous CAT acquisition must be longer than AST source clock period

When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the

CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST

source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,

the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,

ruining the result.

Fix/Workaround

Always ensure that the ATCFG1.max field is set so that the duration of the autonomous

touch acquisition is greater than one clock period of the AST source clock.

6.1.6 aWire

1. aWire MEMORY_SPEED_REQUEST command does not return correct CV

The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to

the formula in the aWire Debug Interface chapter.

Fix/Workaround

Issue a dummy read to address 0x100000000 before issuing the

MEMORY_SPEED_REQUEST command and use this formula instead:

6.1.7 Flash

1. Corrupted data in flash may happen after flash page write operations

After a flash page write operation from an external in situ programmer, reading (data read or

code fetch) in flash may fail. This may lead to an exception or to others errors derived from

this corrupted read access.

Fix/Workaround

Before any flash page write operation, each write in the page buffer must preceded by a

write in the page buffer with 0xFFFF_FFFF content at any address in the page.

6.2 Rev. B

6.2.1 SCIF

1. The RC32K output on PA20 is not always permanently disabled

The RC32K output on PA20 may sometimes re-appear.

Fix/Workaround

Before using RC32K for other purposes, the following procedure has to be followed in order

to properly disable it:

- Run the CPU on RCSYS

- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT

- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as

one

sab

CV 3–

-----------------=

32142DS–06/2013

ATUC64/128/256L3/4U

- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as

zero.

2. PLLCOUNT value larger than zero can cause PLLEN glitch

Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-

nal during asynchronous wake up.

Fix/Workaround

The lock-masking mechanism for the PLL should not be used.

The PLLCOUNT field of the PLL Control Register should always be written to zero.

3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature

The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-

tion in the SCIF memory range.

Fix/Workaround

None.

6.2.2 WDT

1. WDT Control Register does not have synchronization feedback

When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),

Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-

nizer is started to propagate the values to the WDT clcok domain. This synchronization

takes a finite amount of time, but only the status of the synchronization of the EN bit is

reflected back to the user. Writing to the synchronized fields during synchronization can lead

to undefined behavior.

Fix/Workaround

-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock

cycles of both the WDT peripheral bus clock and the selected WDT clock source.

-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the

written value.

6.2.3 SPI

1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0

When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI

module will not start a data transfer.

Fix/Workaround

Disable mode fault detection by writing a one to MR.MODFDIS.

2. Disabling SPI has no effect on the SR.TDRE bit

Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered

when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is

disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer

is empty, and this data will be lost.

Fix/Workaround

Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the

SPI and PDCA.

3. SPI disable does not work in SLAVE mode

SPI disable does not work in SLAVE mode.

Fix/Workaround

Read the last received data, then perform a software reset by writing a one to the Software

Reset bit in the Control Register (CR.SWRST).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45

ATUC256L3U-Z3UT

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32-bit Microcontrollers - MCU UC3L-256KB Flash 64QFN 85C green TRAY

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ATUC256L3U-Z3UT

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